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Author SHA1 Message Date
Raihow Shi ac4648114c mb/google/brask/variants/moli: remove mainboard_vbt_filename in ramstage 
mainboard_vbt_filename() is to decide which VBT to return,
but moli only has one VBT, so it doesn't need this function.

BUG=b:234521809
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 16:06:09 +00:00
Subrata Banik 3f980ca7be soc/intel/alderlake: Drop enable_bios_reset_cpl() function 
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.

Also, drop 1ms delay after setting the BIOS reset CPL.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I87beb444d3910f212a5a627cb449031db6cae38d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64837
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 16:05:40 +00:00
Subrata Banik f4fe21d900 soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init() 
This patch provides an option for CPU programming where coreboot
expected to load second microcode patch after BIOS Done bit is set
and before setting the BIOS Reset CPL bit.

BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I426b38cb1200e60398bc89515838e49ce0a98f06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64836
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 15:34:29 +00:00
Srinidhi N Kaushik 0876103545 vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor Lake 
Add header files generated from FSP 2173_00 source build for Meteor Lake platform.

BUG=b:234701164
TEST=util/abuild/abuild -p none -t google/rex -a -c max

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-06-09 13:49:53 +00:00
Sean Rhodes 0a16291919 soc/intel/alderlake: Add config option for S3 ACPI 
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.

This patch is the Alder Lake equivalent of CB:59024.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2022-06-09 13:48:54 +00:00
Sean Rhodes 843f34e32a soc/intel/apollolake: Correct the maximum number of Heci devices 
Both APL and GLK have 3 Heci devices.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7dc7afb4d2906838a478083b466b36aa78ec49a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-06-09 13:48:32 +00:00
Cliff Huang 0d590b7d91 soc/intel/alderlake: add support for external source clock 
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.

BUG=b:233252409
BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-06-09 13:40:08 +00:00
Cliff Huang 61a442ec01 soc/intel/alderlake: Add support for PCIe slot & device detect timeout 
1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-06-09 13:39:38 +00:00
Jack Rosenthal 76ef18d8ff mb/google/brya: Create ghost4adl variant 
Create new variant of Brya "ghost4adl".

Memory config and device tree was sourced from the schematics
(revision 7670d041f40279b5126990f20ec8f90c0538440c).

GPIO overrides have not been added yet.  This is to be added in a
follow-on CL.

BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2022-06-09 13:35:48 +00:00
Ivy Jian 81d3856755 mb/google/brya/var/agah: Use USB2_PORT_MAX_TYPE_C for Type-C USB2 port 
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`.

The change is required to detect USB2 device on type-C port of Agah boards.

BUG=b:233554817
TEST=build and test USB2 hub could be detected on both the Type-C ports.
=================================================================
usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00
usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
usb 3-3: Product: USB 2.0 Hub
hub 3-3:1.0: USB hub found
hub 3-3:1.0: 4 ports detected
=================================================================

Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 13:35:09 +00:00
Tyler Wang 880b917dc4 mb/google/nissa/var/craask: Generate SPD ID for supported memory part 
Add craaskbowl supported memory parts in mem_parts_used.txt, generate
SPD id for this part.

1. Samsung K3LKBKB0BM-MGCP
2. Hynix   H9JCNNNCP3MLYR-N6E

BUG=b:235134420
TEST=Use part_id_gen to generate related settings

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 13:34:49 +00:00
Terry Chen 54f83c90b0 mb/google/brya: Add memory parts for Crota 
Add a mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.

DRAM Part Name                 ID to assign
MT62F1G32D4DR-031 WT:B         0 (0000)
MT62F512M32D2DR-031 WT:B       1 (0001)
H9JCNNNBK3MLYR-N6E             1 (0001)
H9JCNNNCP3MLYR-N6E             0 (0000)
K3LKBKB0BM-MGCP                2 (0010)
K3LKLKL0EM-MGCN                3 (0011)
H58G56AK6BX069                 2 (0010)

BUG=b:233830713
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-09 13:34:33 +00:00
Arthur Heymans 2392674780 mb/qemu-armv7: Initialize cbmem 
Change-Id: I607205a0d44c71eb26031ced7a8af303efacd6f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-06-09 13:33:58 +00:00
Hsuan Ting Chen 607b39c593 libpayload: Add commonlib/bsd/elog and its dependency 
Add commonlib/bsd/elog dependency in libpayload. This will allow other
payloads (e.g. depthcharge) to implement their own eventlog read and
write utilities.

Also include commonlib/bsd/elog.c source to libc-srcs. This ensure
payloads could utilize commonlib elog helper functions.

Change-Id: I64d0fdd2a8eff1d89a1ac451d37b61787b5564e7
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2022-06-09 13:33:35 +00:00
Felix Singer 7d8df61774 mb/aopen/dxplplusu/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax 
Replace `LNotEqual(a, b)` with `a != b`.

Change-Id: Iae3343e66906a8123b3d8de2b67948f286e4ad32
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:23:40 +00:00
Felix Singer 37a89d519d ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax 
Change-Id: I8a0f18d37c065827a0f5b54f24ea1fcde497c504
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:23:21 +00:00
Felix Singer 9a351fb445 ec/lenovo/h8/acpi: Replace And() with ASL 2.0 syntax 
Change-Id: Id600bcb3fad35455adffe11a8105ad2590e83feb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:21:38 +00:00
Felix Singer 32283a86cf ec/lenovo/h8/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: Idfc08803946cc2d4537db4be8d1bc07e48aa6fed
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:20:48 +00:00
Felix Singer 26caf387ff mb/google/slippy: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I63b8b8a086e2c5ede765855b3c803206edf87690
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:20:28 +00:00
Felix Singer 54d0c99523 mb/google/kahlee: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:20:00 +00:00
Felix Singer cc62b50935 mb/google/cyan: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: Ib8719143a5a217173b34931e9c0ef02e9895d0a5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:19:45 +00:00
Felix Singer cdba42c69c ec/smsc/mec1308/acpi: Replace LLessEqual(a,b) with ASL 2.0 syntax 
Replace `LLessEqual(a, b)` with `a <= b`.

Change-Id: Ib4e81ea95c6fda0e8f8640671db5ce56f3a1b474
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:19:14 +00:00
Felix Singer 9bfbbe8b17 ec/smsc/mec1308/acpi: Replace LGreater(a,b) with ASL 2.0 syntax 
Replace `LGreater(a, b)` with `a > b`.

Change-Id: I04f3cc2dbba59d732c9c52a4b90a32481f9da337
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:18:43 +00:00
Felix Singer 6929403b88 ec/smsc/mec1308/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax 
Replace `LNotEqual(a, b)` with `a != b`.

Change-Id: Ib34dc8d84815d0885f30b3ea8ceb2fb95a833d50
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:18:24 +00:00
Felix Singer 8353e9a8a7 ec/smsc/mec1308/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: Ib96cf05f575a2868b2ad0c00fd5486d6e2c5d90a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:17:52 +00:00
Felix Singer 0375b828f9 ec/quanta/it8518/acpi: Replace LGreater(a,b) with ASL 2.0 syntax 
Replace `LGreater(a, b)` with `a > b`.

Change-Id: I86a11ab5d2667661af3491174001001e644083e3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:17:21 +00:00
Felix Singer a484bba667 ec/smsc/mec1308/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntax 
Replace `LGreaterEqual(a, b)` with `a >= b`.

Change-Id: If83d7fe29d112ba0ed0f72798f2b5436ecf0a6a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:16:49 +00:00
Felix Singer 10ca0ab512 ec/quanta/it8518/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: Ief1fe60116645d0cdad9e7ac600bc1062b54b40d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:16:23 +00:00
Felix Singer 7bf014f0ad ec/smsc/mec1308/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual(a, b)` with `a == b`.

Change-Id: Ic58e22046aa13549747692f4b21184cf573aa4d3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:15:56 +00:00
Felix Singer d40d0b0398 ec/quanta/it8518/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntax 
Replace `LGreaterEqual(a, b)` with `a >= b`.

Change-Id: I99cc4cf08ad74f2cb84e0ad16e615e03bbf388af
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:15:37 +00:00
Felix Singer 3f53ee3269 ec/quanta/it8518/acpi: Replace Divide(a,b,,c) with ASL 2.0 syntax 
Replace `Divide (a, b, , c)` with `c = a / b`.

Change-Id: I9b8262396755197dfbe044e3dc6a6a75c903f093
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:15:14 +00:00
Felix Singer 1e96554846 ec/quanta/it8518/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual(a, b)` with `a == b`.

Change-Id: I6732fd876524feab924a58434bec381dcdb87bce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:14:38 +00:00
Felix Singer f1f861ebf5 ec/quanta/it8518/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: Ied407753ee3bb024c8c0350c45312c337ac799e5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:14:13 +00:00
Felix Singer d5d4b4459f ec/quanta/ene_kb3940q/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: Ic04ce82fbfd36bbd2e0cfda1a92ca0a18e1fcd73
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:13:31 +00:00
Felix Singer 6119303a39 ec/kontron/it8516e/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I81e976de964f6ae3528884debaf2b24ddf8ed28a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:13:15 +00:00
Felix Singer c0ce14cc04 mb/google/jecht/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:10:54 +00:00
Felix Singer fc12747ac3 mb/google/jecht: Replace Multiply(a,b,c) with ASL 2.0 syntax 
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:10:38 +00:00
Felix Singer 9f5f793e67 mb/google/slippy/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntax 
Replace `LGreaterEqual(a, b)` with `a >= b`.

Change-Id: I5c16893b9c98f36fd2c210ed301c2ebb65f95368
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:10:14 +00:00
Felix Singer db2fdc298c mb/google/kahlee/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntax 
Replace `LGreaterEqual(a, b)` with `a >= b`.

Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:09:56 +00:00
Felix Singer 105d1185bb mb/google/slippy/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax 
Replace `LNotEqual(a, b)` with `a != b`.

Change-Id: I61ef7b53e851f4c2367cba43ff76b200e9490ad2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:09:22 +00:00
Felix Singer e18277a998 mb/aopen/dxplplusu/acpi: Replace LGreater(a,b) with ASL 2.0 syntax 
Replace `LGreater(a, b)` with `a > b`.

Change-Id: If482b2ad4ba7d4ed1ca8c0695690ede153ed1e2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:08:55 +00:00
Felix Singer 6c84832e9f mb/google/jecht/acpi: Replace LGreaterEqual(a,b) with ASL 2.0 syntax 
Replace `LGreaterEqual(a, b)` with `a >= b`.

Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:08:29 +00:00
Felix Singer e0545cc2bb arch/x86/acpi: Replace ShiftLeft() with ASL 2.0 syntax 
Change-Id: I493d686fb122fb47f0b4dcf34e3635518770f97f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:07:18 +00:00
Felix Singer c9d6e81894 arch/x86/acpi: Replace ShiftRight() with ASL 2.0 syntax 
Change-Id: Iaa99d9dc4cf12a7431be1610d339cf78116f8bea
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:06:55 +00:00
Felix Singer b2d8807392 superio/winbond/w83667hg-a: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual(a, b)` with `a == b`.

Change-Id: I033f73e6552746c6899e46ee4d619ab47cb3d55b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:05:56 +00:00
Felix Singer 3cfbe8a094 sio/winbond/w83627hf/acpi: Replace LNotEqual(a,b) with ASL 2.0 syntax 
Replace `LNotEqual(a, b)` with `a != b`.

Change-Id: I24cf4fd70e887c14006975f494be63c34f8a75e6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:05:29 +00:00
Felix Singer d67ed5921f sio/winbond/w83627hf/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: I9344e34058a1dd8b951d273e53e3c229a0ec07b4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:04:45 +00:00
Felix Singer 3f37d7afcb superio/winbond/w83627hf/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual(a, b)` with `a == b`.

Change-Id: I3833a3a341bd64191cc0b811ca80e96a359307a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:04:30 +00:00
Felix Singer b1b9c73902 superio/acpi: Replace LLess(a,b) with ASL 2.0 syntax 
Replace `LLess(a, b)` with `a < b`.

Change-Id: I407d061ac7664d4910b8759fd1a72eab133b6e22
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:04:10 +00:00
Felix Singer 8ef8a3e3c1 superio/acpi: Replace LEqual(a,b) with ASL 2.0 syntax 
Replace `LEqual(a, b)` with `a == b`.

Change-Id: Ia09c54465af47f5779917ed71bb3ea148864dfd1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
 2022-06-09 09:03:45 +00:00