Commit Graph

37027 Commits

Author SHA1 Message Date
Michael Niewöhner 47fd4fa617 mb/system76/lemp9: gpio: rework comments
Rework the comments:
  - fix wrong gpio / net names
  - convert all comments to <gpio> / <net name>
  - add more information where appropriate

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:56:58 +00:00
Michael Niewöhner 90041ef886 mb/system76/lemp9: gpio: convert PAD_CFG_TERM_GPO to PAD_CFG_GPO
Convert PAD_CFG_TERM_GPO with pull "NONE" to its shorter equivalent
PAD_CFG_GPO.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9ed4d97ba184fa3e72425d5d16042a142b0640b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43649
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:55:43 +00:00
Michael Niewöhner dd70d28ef7 mb/system76/lemp9: gpio: disable unused pad for INTP_OUT
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is
currently unused in coreboot. It isn't a requirement for PD to work.
Disable it for now.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:52:10 +00:00
Michael Niewöhner 78cb41798e mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-ups
Disable internal pull-ups for SATAXPCIE pads since there are external
ones at the M.2 slot's PEDET pins.

Test: both, SATA and NVME devices work fine on both slots

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:51:54 +00:00
Michael Niewöhner 1ba8a50df3 mb/system76/lemp9: gpio: configure unused pads
There are pads being unused for various reasons:
  a) missing board support (DeepSx: SUSWARN#)
  b) unneeded feature ID pins
     - currently no known device models without keyboard backlight
     - currently no known device models without TPM
  c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time
  d) DDR_TYPE_*: there is only one known ram model
  e) strap-only pads
  f) unconnected pads

Configure them as NC with appropriate pull-up if no external pull exists.
The latter was checked by schematics and looking at the board.

When any of the unused ID pins is needed in the future, they can be
reactivated easily (configure as GPI).

Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:51:34 +00:00
Jamie Ryu d10a10befd mb/google/volteer: Update flashmap descriptor for CSE Lite FW update
To support CSE Lite firmware update, CSE RW partition is extracted from
CSE blob binary and added to FW_MAIN_A and FW_MAIN_B.

CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and
FW_MAIN_B is increased to avoid an overflow.

BUG=b:140448618
TEST=build with me_rw binary blob for volteer and boot to kernel.

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 22:06:39 +00:00
Michael Niewöhner f0b6b30c46 mb/system76/lemp9: enable TPM
L140CU has a TPM2 connected via SPI. Add the TPM device to the
devicetree and enable it.

According to Intel doc#615170-001, PIRQ is required for SPI TPM to work.
Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as
TPM interrupt in Kconfig.

Note: The PCH maps either LPC TPM or SPI TPM to the same address and
handles either LPC or SPI communication transparently. Thus we can use
MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address.

Tested, but only polling works currently, because there is some upstream
issue with the tpm_tis module in current Linux kernels. [1]

[1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 21:10:13 +00:00
Angel Pons 803bd3c682 security/intel/txt/getsec.c: Do not check lock bit
This allows calling GETSEC[CAPABILITIES] during early init, when the MSR
isn't locked yet.

Change-Id: I2253b5f2c8401c9aed8e32671eef1727363d00cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-30 19:26:48 +00:00
Angel Pons 7fdd1faf2d security/intel/txt: Add missing definitions
Change-Id: I3ca585429df318c31c2ffd484ec91a7971f18f27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44882
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 19:25:55 +00:00
Angel Pons 99b2f30bd0 cpu/intel/haswell: Set LT_LOCK_MEMORY MSR on finalize step
This is a security lock and is required for TXT, among other things.

Tested on Asrock B85M Pro4, still boots.

Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 19:25:43 +00:00
Kevin Chiu 144c5aeca2 mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for burnet/esche
Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB

BUG=b:165956924
BRANCH=kukui
TEST=emerge-jacuzzi coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30 17:03:35 +00:00
Patrick Rudolph 9256e51f48 cpu/x86/smm/smmhandler: Fix x86_64 assembly exit
Fix an issue the assembler didn't warn about to fix a crash on real
hardware. qemu didn't catch this issue either.

The linker uses the same address for variables in BSS if they aren't
initialized in the code. This results in %edx being set to the value
of %eax, which causes an exception restoring IA32_EFER on real
hardware.

Tested on qemu with KVM enabled.

Change-Id: Ie36a88a2a11a6d755f06eff9b119e5b9398c6dec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-30 14:48:35 +00:00
Angel Pons 2e29c3b0d5 sb/intel/bd82x6x: Factor out common ME functions
We can now factor out the essentially duplicated ME functions.

We include a .c file to preserve reproducibility. This is needed because
there are two different `mei_base_address` global variables, and we have
to access the same variables in order for builds to be reproducible.

The duplicate global in `me.c` and `me_8.x.c` will be completely gone
once this new `me_common.c` file becomes a standalone compilation unit.
We are wrapping some things in static inline functions, as they won't be
directly accessible anymore after moving to a separate compilation unit.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I057809aa039d70c4b5fa9c24fbd26c8f52aca736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
2020-08-29 20:15:37 +00:00
Matt DeVillier 62e883d73b util/inteltool: Add support for Comet Lake-U
Add support for 10th-gen/Comet Lake-U based boards:
- add PCI IDs for host bridge, IGD, LPC devices
- add support for dumping GPIOs, PCRs, etc

Tested on an unbranded CML-U board running AMI firmware

Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-29 13:41:04 +00:00
Edward O'Callaghan b656e9b71e PCI IDs: Add PCI ID for CML DPTF/DTT PCI device
This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.

CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.

BUG=b:158986928
BRANCH=puff
TEST=builds

Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
2020-08-29 01:59:02 +00:00
Kangheui Won 07de908373 amd/picasso/psp_verstage: add vboot rsa function
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa
signature against digest using PSP svc.

This function will be later used by vboot to accelerate rsa
verification.

BUG=b:163710320, b:161205813
TEST=build zork firmware with vboot modification, confirm it's booting
and boot time is reduced by ~230ms.

Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 21:56:08 +00:00
Kangheui Won 4c875c8a5d Update vboot submodule to upstream master
Updating from commit id 3932b1c:
2020-08-19 02:09:04 +0000 - inclusive: change usage of
blacklist/whitelist

to commit id fefcaa6:
2020-08-24 04:32:03 +0000 - vboot: adjust VB2_SECDATA_KERNEL_FLAGS in
non-recovery path

This brings in 2 new commits.

Change-Id: Ia3ff764537b91f76ba6fa3ba2646638964800510
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-08-28 21:55:20 +00:00
Hung-Te Lin d04b388381 libpayload: cbgfx: Support buffered I/O
For payloads with UI based on CBGFX, they usually start by calling
clear_canvas or clear_screen and then draw the UI elements. However,
that makes the screen flicker.

A typical solution is to identify and minimize the area to redraw.
However for payloads with complicated UI and do not care about latency,
an alternative is to enable buffered I/O.

The new enable_graphics_buffer() will redirect all graphics I/O
into an invisible working buffer. To flush (redraw) the buffer to the
real screen, call flush_graphics_buffer(). To stop buffering, call
disable_graphics_buffer().

BUG=None
TEST=Add the enable, flush and disable calls to payload 'depthcharge',
     built a firmware and boots into Chrome OS recover UI. No more
     flickering. The average rendering time on x86 platform is 1.2ms.

Change-Id: Id60a2824fd9e164feae16b92b68b003beabea8d3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44654
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 21:40:58 +00:00
Kane Chen 6d7996439f mb/google/zork: Modify USI_RESET_L GPIO 140 to be active to low
Modify USI_RESET_L GPIO_140 in touchscreen power on/off sequence
to be active low.

BUG=b:160126287
BRANCH=Zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I53dd872fdacb95cda43f297d2c3f9c6723b27bad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 19:04:09 +00:00
Matt Papageorge 48b2b2b8c1 mb/google/zork: Disable SATA device for all Zork platforms to save power
SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting

BUG=b:162302027

Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 17:54:19 +00:00
Matt Papageorge b87effe1dd soc/amd/picasso/romstage: Set SATA enable UPD if controller is enabled
FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.

BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.

Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 17:50:50 +00:00
Nikolai Vyssotski b1c7ed326a vc/amd/fsp/picasso: Add FSP-M UPD enable_sata to 0xC7 to match FSP
BUG=b:162302027
BRANCH=zork

Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I4b5c3b351b6232f8b0418ead47d87aaddd350668
Cq-Depend: chrome-internal:3201648
Cq-Depend: chrome-internal:3202602
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 17:49:10 +00:00
Johnny Lin 6da1710fbc mb/ocp/deltalake: Configure FSP DCI via VPD
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.

Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-28 17:45:24 +00:00
Jonathan Zhang d5f24dd99b vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc
Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.

In addition, there are some changes to HOB data structures.

Update UPD and HOB header files and adapt soc accordingly.

TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 17:44:46 +00:00
Rob Barnes 0f51ff72e4 mb/google/zork/woomax: Remove unused memory parts
These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.

Command to generate files:
	go build gen_part_id.go
	local variant=woomax
	./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt

BUG=b:165611555
TEST=none

Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28 16:16:58 +00:00
Rob Barnes 7dcfd1b56a mb/google/zork/berknip: Remove unused memory part IDs
These parts have not been used in any berknip devices. Removing
so IDs can be assigned more efficiently.

Command to generate files:
	go build gen_part_id.go
	local variant=berknip
	./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt

BUG=b:165611704
TEST=none

Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 16:16:42 +00:00
Rob Barnes c9458ddb67 mb/google/zork/dirinboz: Remove unused memory part IDs
These parts have not been used in any dirinboz devices. Removing
so IDs can be assigned more efficiently.

Command to generate files:
	go build gen_part_id.go
	local variant=dirinboz
	./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt

BUG=b:165611271
TEST=none

Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 16:16:35 +00:00
Aaron Durbin ceb87150d4 soc/intel/tigerlake: add ddr4-spd-empty.hex
In generating the potential spds the ddr4-spd-empty.hex was
accidentally omitted.

Generated from:
go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \
	util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL

Change-Id: Ic8b9449830fb5405ebf138ebd54f41b0f76ba584
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44908
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 16:13:39 +00:00
Rob Barnes 55ccd5b873 mb/google/zork: Switch zork to use spd_tools
Switch all zork boards to use generated generic SPDs from spd_tools.

HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.

picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.

Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
	n=$(basename ${b});
	if [ "${n}" = "baseboard" ]; then
		continue
	fi
	go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
		src/mainboard/google/zork/variants/${n}/spd \
		src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
	done

BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 15:58:34 +00:00
Nick Vaccaro 8da998c2b0 mb/google/volteer: add initial SPDs for Elemi variant
Add mem_list_variant.txt, a list of memory parts used by elemi SKUs.
Add dram_id.generated.txt, a list of dram id's to use for each memory part.
Add Makefile.inc, to specify DDR4 and build the SPD file list.

BUG=b:165461530
TEST=none

Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 14:44:23 +00:00
Rob Barnes 8283ae6bab util: Add memory parts needed by zork boards
Add memory parts needed by zork boards. Attributes are derived from data
sheets.

BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 14:29:44 +00:00
Nick Vaccaro 913ea9278f util/gen_spd: translate DeviceBusWidth to die bus width
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.

Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive

BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.

Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28 14:20:30 +00:00
Hung-Te Lin 2afee12991 src: Remove incorrect x86 exception not from TS_DONE_LOADING description
The TS_DONE_LOADING timestamp description had "(ignore for x86)", but
the implementation in vboot_logic.c will read every bytes, so the
timestamp is correct even for devices with memory mapped boot device
(e.g., x86).

To prevent confusion we should remove the 'ignore for x86' message.

BUG=None
TEST=make -j
BRANCH=None

Change-Id: I01d11dd3dd0e65f3a17adf9a472175752c2b62bc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 06:07:37 +00:00
Nick Vaccaro c5428a990a mb/google/volteer: update Delbin SPD for H9HCNNNCPMMLXR-NEE
I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.

$ go run ./util/spd_tools/lp4x/gen_part_id.go \
	src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
	src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt

Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.

This change updates that discrepancy in Delbin's memory Makefile.inc.

BUG=none
TEST=none

Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 05:01:40 +00:00
Aaron Durbin 0245f43bcd Revert "util: update lp4x gen_part_id tool to include memory type"
This reverts commit eb7a1dd80e.

MEMORY_TYPE = lines in Makefiles are not longer needed. Drop it.

Change-Id: I96ac39a30555a870e7778a0e71d738407b6b89ef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44895
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 05:01:31 +00:00
CK Hu ba616438e9 soc/mediatek/mt8192: Use SPI-NOR as flash controller
Add a SPI-NOR flash controller which supports pio mode.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-28 04:44:56 +00:00
Rob Barnes a662648a7f util: Add support to spd_tools for fixed id
For boards that have already assigned memory ids, there needs to be a
way to fix parts to a specific id. After assigning all the fixed ids the
tool still attempts to minimize the SPDs entries. Since a fixed ID could
be anywhere, gaps can be created in the list. So an empty SPD entry is
created to fill the gaps in the list until they are used.

BUG=b:162939176
TEST=Generate various outputs

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1f8ea1ff4f33a97ab28ba94896a1054e89189576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-28 04:36:55 +00:00
Nick Vaccaro e905753afd util: rename lp4x spds to include "lp4x-" in name
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).

BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..

Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 04:36:18 +00:00
Nick Vaccaro 48fc1640a8 util: volteer/dedede: move generic SPDs to common location
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location.  This CL moves
the generic SPDs to the new location.

Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".

Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".

Move TGL DDR4 and LPDDR4x generic SPDs into a common location.

Move JSL DDR4 and LPDDR4x generic SPDs into a common location.

Change the volteer/spd/Makefile.inc to use the new path for the spds.

Change the dedede/spd/Makefile.inc to use the new path for the spds.

BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.

Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28 04:35:56 +00:00
Rob Barnes c19140b49f util: Add check for duplicate entries in mem parts json
Check for duplicate entries in mem parts json file.

BUG=b:162939176
TEST=Verified that tool throws error when there is a duplicate.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7c638c7938958727cfc832e7b4556acbc04b0ca4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44478
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 22:39:32 +00:00
Julius Werner 644a512e56 symbols: Change implementation details of DECLARE_OPTIONAL_REGION()
It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-27 22:11:17 +00:00
Rob Barnes 8cc80d5e50 util: Add Picasso and Pollock platforms to spd_tools
PCO = Picasso
PLK = Pollock

BUG=b:162939176

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I43b74f68871062112f53fbbef8a170db53734b3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44477
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 21:41:30 +00:00
Rob Barnes a2e431331c util/spd_tools: Support comments in json
Allow comments in json file for better documentation. Comments must be
on seperate line.

BUG=none
TEST=Injest global_ddr4_mem_parts.json.txt with comments

Change-Id: I51295408d4f916708e4ed5bc42d5468ccdc68a6b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-27 21:41:18 +00:00
Rob Barnes 196e9c0021 util/spd_tools: Remove intel subfolder
Move ddr4 and lp4x to spd_tools root folder. The tool now applies to non
intel platforms.

BUG=b:162939176
TEST=Run tool

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0941ea036d760ee27eb34f259f4506a4b7584bee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 20:14:34 +00:00
Ravi Sarawadi 1860cd460a mb/google/volteer*: Enable IPU
Enable IPU for Volteer and Volteer2 variants for MIPI camera.

BUG=165340186
BRANCH=None
TEST=IPU is enabled and shows in lspci.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 18:14:39 +00:00
David Wu 81a2f45bd2 mb/google/puff: Update psyspl2 to 97% of adapter rating
Set psyspl2 to 97% of adapter rating, based on our experiment results.

BUG=b:160676773
TEST=Built and check firmware log.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2020-08-27 05:00:50 +00:00
Tan, Lean Sheng 21910f00de soc/intel/common: Include Elkhart Lake SA IDs
Add additional Elkhart Lake specific SA IDs.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I41af9b17b8121f3b47f2242d9beeec297893b378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40854
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27 03:22:03 +00:00
Tan, Lean Sheng 7337bdcbca soc/intel/common: Add Elkhart Lake B0 CPU ID
Add Elkhart Lake B0 CPU ID.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I90fab9a6392443005ee7224049931c687cb77c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-08-27 03:21:32 +00:00
Aaron Durbin 48697fe009 mb/google/zork: meet SAR depedencies
DRIVERS_WIFI_GENERIC is a dependency for these SAR settings.
However, coreboot.org builders are not failing, but chromium
builders are only for serial configurations. It's not clear as
to why. Either way correct this.

BUG=b:159304570

Change-Id: I978b622a3a5a2490b0e3aaa14c24807d5afdff9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44825
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26 14:54:53 +00:00
CK Hu 4c44108423 soc/mediatek: Include addressmap.h in gpio_common.h
The gpio_common.h needs EINT_BASE from addressmap.h.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I20834e38343410526da0a489fed907acbf479d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-08-26 08:52:53 +00:00