Commit Graph

22207 Commits

Author SHA1 Message Date
Martin Roth 2d1e0eb8a7 payloads/coreinfo: Free buffer before returning
Fixes coverity issue 1373370 - Resource leak

Change-Id: I71e0d3ae7f9152e1f89f8b3206526f0d344e0351
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-11 16:23:52 +00:00
Marc Jones 6223a200aa kahlee: Add RO_VPD region in FMAP
The RO_VPD region is required for ChromeOS.

BUG=b:65408869
TEST=Build and check coreboot.rom with fmap_decode.

Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11 01:30:20 +00:00
Aaron Durbin 5a1f9a87cb cpu/x86/mp_init: remove adjust_cpu_apic_entry()
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.

Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-11 01:17:45 +00:00
Nico Huber 0b80bd1cf4 nb/intel/i945: Clear timeout bits after disabling watchdog
Even with the watchdog disabled, these bits influence other hardware
blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet
before they started).

Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-10 17:49:27 +00:00
Kyösti Mälkki 3b4b069a0c AGESA binaryPI: Remove heapmanager from romstage
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved
from romstage to ramstage, heapamanager in romstage
is no longer needed.

Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10 03:23:32 +00:00
Kyösti Mälkki f51c5fd655 sb/intel/common: Fix HAVE_DEBUG_SMBUS
Failed to build with DEBUG_SMBUS=y, slave_bytes is
not initialized until inb().

Change-Id: Ia53717756ed74bc797a9529e36fc6965d6872101
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21470
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-10 03:22:43 +00:00
Furquan Shaikh c18aa1c777 vboot: Use "Google_" as VBOOT_FWID_MODEL prefix if CHROMEOS is set
CONFIG_MAINBOARD_VENDOR is customizable by OEM for Chrome OS
devices. However, VBOOT_FWID_MODEL indicates the firmware vendor and
hence if CHROMEOS is selected, then VBOOT_FWID_MODEL should always
prefix "Google_" instead of CONFIG_MAINBOARD_VENDOR.

BUG=b:65493192

Change-Id: I0a2280bfd6d535586bc14d9a3c4a8198287f08bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-09-10 02:20:55 +00:00
Martin Roth de60e603e8 amdfw: Clean up makefiles a bit more
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig.
- Remove 2nd set of variables that are duplicates of the first set.
- Delete duplicate set of Prerequisites

Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21451
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-10 00:48:39 +00:00
Kyösti Mälkki b5d998b9e0 sb/intel/common: Add HAVE_DEBUG_SMBUS
Change-Id: Ifb1a1eff71968f31af9004ff00717f202d3ec29e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09 12:59:45 +00:00
Kyösti Mälkki 1e39236f96 sb/intel/common: Fix i2c block command
Coding style, sync implementation with SMBus counterpart.

Change-Id: I75f24e2308de945fc03289636ae914bb87070838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09 12:58:58 +00:00
Kyösti Mälkki c17e855da0 sb/intel/common: Tidy up SMBus block commands
I forgot to push these changes before merging commit
  1b04aa2 sb/intel/common: Fix SMBus block commands

Change-Id: I7217f8c0cc78f2161faf31a4c49e3e9515026d15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-09 12:58:49 +00:00
Kyösti Mälkki 916b331a8d ACPI S3: Handle LATE_CBMEM_INIT boards
Followup removes inlined acpi_is_wakeup_s3() from PRE_RAM,
and new implementation depends of CAR_GLOBAL.

Change-Id: Iea1c5ab2175f8d496baa09bd6137cacc912df2cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09 11:18:10 +00:00
Kyösti Mälkki d35c06d09e sb/amd: Support CBMEM_TOP_BACKUP
Change-Id: I8d2005e4f2aa5a3b46e30f52556ee66aeb3d10cc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-09 11:16:28 +00:00
Martin Roth b617e32bb9 soc/amd/stoneyridge: Update amdfw build
- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.

BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.

Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-08 21:11:52 +00:00
Kevin Chiu 348a6d519c soc/intel/braswell: add USB2 PHY PERPORTRXISET UPD
Adapted from Chromium commits 59938a0, 5a4ea6e, 88999de.

Add UPD to config USB2 PERPORTRXISET for D-stepping BSW SoC.
Ensure PerPortRXISet UPD offsets align with FSP.
Ensure UPD values not defined in devicetree.cb are referred from *.dsc.

Original-Change-Id: Ib0cdee47692e492a78c34e2dd192447b92253e35
Original-Change-Id: If0d8419d4c70864bd385b5699e0e6d1ec515d26a
Original-Change-Id: I3a1d688282303e8c367620ac8bb3e2cba7ab3dcf
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: I87eda6ea6688931f1a1b069c38ffc515398ad396
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 21:09:48 +00:00
Matt DeVillier 2c8ac22873 soc/intel/braswell: Add USB2 phy setting override
Adapted from Chromium commit 9756af8.

Create hook function to override USB2 phy setting from board level.

Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 21:09:19 +00:00
Matt DeVillier 143a836e5a soc/intel/braswell: Add SoC stepping identify helper
Adapted from Chromium commit 9756af8.

Add SOC helper to identify BSW SoC stepping.  Will be used to
override USB2 phy setting based on stepping in subsequent commit.

Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 21:09:05 +00:00
Divagar Mohandass 0c68530f15 soc/intel/braswell: Add I2C clock config options
Cherry-pick from Chromium commit e3c1ec2.

This change includes
- FSP config parameters to configure I2C clock speed.
- Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz.

Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 21:07:53 +00:00
Matt DeVillier 77c01e1f2f drivers/intel/fsp1_1: Adjust check for FSP header revision
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.

This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).

TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).

Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08 21:07:32 +00:00
Shaunak Saha bd427803ab soc/intel/common/block: Common ACPI
This patch adds the common acpi code.ACPI code is very similar
accross different intel chipsets.This patch is an effort to
move those code in common place so that it can be shared accross
different intel platforms instead of duplicating for each platform.
We are removing the common acpi files in src/soc/intel/common.
This removes the acpi.c file which was previously in
src/soc/common/acpi. The config for common acpi is
SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's
Kconfig file in order to use the common ACPI code. This patch also
includes the changes in APL platform to use the common ACPI block.

TEST= Tested the patch as below:
1.Builds and system boots up with the patch.
2.Check all the ACPI tables are present in
  /sys/firmware/acpi/tables
3.Check SCI's are properly working as we are
  modifying the function to override madt.
4.Extract acpi tables like DSDT,APIC, FACP, FACS
  and decompile the by iasl and compare with good
  known tables.
5.Execute the extracted tables in aciexec to check
  acpi methods are working properly.

Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-08 19:01:04 +00:00
Mario Scheithauer af896d071b siemens/mc_apl1: Disable internal UARTs
APL internal UARTs are not used on this mainboard.

Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08 10:50:40 +00:00
Mario Scheithauer b83858af5b siemens/mc_apl1: Set bus master bit for on-board PCI device
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().

Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08 10:50:30 +00:00
Kyösti Mälkki 65e54662e3 intel/car: Fix stack guard placement
Make sure guard placement is above CAR region.

Change-Id: I780cdc0b2a549e7ac4b23b0870619f5648a644e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21313
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08 03:26:55 +00:00
Kyösti Mälkki f8e9449df0 AGESA: Drop old ACPI S3 resume path
Fixed ACPI S3 support will use POSTCAR_STAGE and no longer
uses the code removed here.

Change-Id: I180adaaccce5f0caabcdcd67f3000a21295b0ecf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 03:19:38 +00:00
Kyösti Mälkki 740afc4dde arch/x86/postcar: Support CBMEM_TOP_BACKUP
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE
for MTRR setup after adding this file in the build.

Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08 03:18:15 +00:00
Kyösti Mälkki a7421fb9cb arch/x86 postcar: Fix use with stage_cache
Postcar failed when loading from stage_cache, if
romstage did not pass same pcf->stack on normal
and resume paths.

Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08 03:18:04 +00:00
Kyösti Mälkki d87e4b3469 stage_cache: Add rmodule params in metadata
The change allows to update rmodule parameters after
it has been loaded from stage cache.

Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08 03:17:52 +00:00
Subrata Banik 534b23639b soc/intel/skylake: Create acpi_get_sleep_type() to get previous sleep state
This patch implements soc function to get previous sleep state
using chipset_power_state global structure.

acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.

Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-08 01:15:47 +00:00
Pratik Prajapati 6dc148a42b soc/intel/common/sgx: Fix null pointer dereference warning from klocwork
Fix the warnings of klocwork scan.
e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159"

Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-07 20:05:13 +00:00
Julius Werner 2be64048c1 google/gru: Re-enable 3V rail GPIO on Scarlet
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.

Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-09-06 23:26:47 +00:00
Kyösti Mälkki 64df52e269 AGESA f14: Work around soft-resets
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.

Without the workaround, raminit fails on soft resets.

Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:23:19 +00:00
Kyösti Mälkki 081b66951f mainboard/lippert: Refactor SEMA watchdog message
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.

Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.

Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:18:10 +00:00
Kyösti Mälkki 8a8386eeb9 asus/kgpe-d16: Add romstage_handoff
Fix regression caused by commit

  9e94dbf ACPI: Get S3 resume state from romstage_handoff

Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.

Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:16:42 +00:00
Kyösti Mälkki c2a921bec1 asus/kcma-d8: Add romstage_handoff
Fix regression caused by commit

  9e94dbf ACPI: Get S3 resume state from romstage_handoff

Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.

Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-09-06 22:16:25 +00:00
Kyösti Mälkki a26377b063 asus/kcma-d8 kgpe/d16: Fix regression for shutdown
Fix regression caused by commit:

  714709f AMD fam10 ACPI: Use common fixed sleepstates.asl

Adding common sleepstates.asl got lost in rebase process.

Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-06 22:16:05 +00:00
Harsha Priya 130b4a29eb mb/google/{poppy,soraka,eve}: Add imon and vmon params for Max98927 codec
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.

BUG=b:36724448
TEST=After boot, the register dump for  Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.

Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 19:00:52 +00:00
Harsha Priya 1517735714 driver/i2c/max98927: Add imon and vmon params
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.

BUG=b:36724448
TEST=After boot, the register dump for  Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.

Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 19:00:41 +00:00
Kyösti Mälkki eab5c12ee0 util/cbmem: Pretty print STAGEx_META and _CACHE
Also align entries without name with additional indents.

Change-Id: Ia6aa303daa11e6aec249232aadf4e346bad659d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 17:25:23 +00:00
Nick Vaccaro 900ecbf6e1 soc/intel/cannonlake: remove duplicate uart.c from bootblock
There was already a uart.c added to bootblock. Remove the
duplicate addition.

Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06 17:06:04 +00:00
Lijian Zhao 6d7063c2ac soc/intel/cannonlake: Add Vboot/ChromeOS support
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.

Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 16:53:37 +00:00
Rizwan Qureshi 8688536ca2 mb/google/soraka: enable AER for PCIe root port 0
Enable PCIe Advanced Error Reporting for PCIe root port 0.

Change-Id: I76742801e84449d0910ddadf31d39597df3263b9
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 16:40:01 +00:00
Rizwan Qureshi 6ab4ed40d3 soc/intel/skylake: Add config for enabling PCIe AER
Add a config for enabling/disabling Advanced Error Reporting feature
for PCIe root ports.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06 16:39:58 +00:00
Nicola Corna 33f1273f9f tint: Use the current time as random seed
Previously the random seed was fixed, which led to the same sequence of
blocks for each run.

Now that libpayload has time(), no change is needed in the function
rand_init() of tint.

Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-06 11:53:57 +00:00
Patrick Georgi e41b0d09ba util/testing: Don't keep tegra lp0 build results
We don't actually care for them on our testers, just that the files
can be built.

Change-Id: Ib656a085d70e2aeb1601f1943ad8581af3133839
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21420
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-06 11:36:27 +00:00
Kyösti Mälkki 3a19a1c38e AGESA vendorcode: Auto include-dirs
AGESA internal headerfiles are allover the place. Luckily, they
have unique names within the Proc/ tree so include every existing
directory in undefined order.

Change-Id: I86f080e514391a3f0f05d379d24d490ce075060e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-06 09:31:38 +00:00
Patrick Georgi 2997a97a3a 3rdparty/vboot: update to latest master
Besides some internal changes that won't have much effect on coreboot,
the newer version also supports building host tools on systems that
self-designate as i686.

Change-Id: I823bad862805cdec1dfecc8ba046f73ac206d3e8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06 08:24:04 +00:00
Patrick Georgi cdd3a4327b util/testing: Also test-build tegra's lp0 resume code
The regular build doesn't build it, so it fails every now and then due
to changes in its dependencies.

Make sure we notice these early.

Change-Id: I0603b22887487d8871611d91e6f8ab0ec210bff1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-09-06 08:23:41 +00:00
Kyösti Mälkki ced3a0c249 Revert "soc/intel/cannonlake: Add dummy ACPI DSDT table"
This reverts commit 6c0f3c7ee1.

Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.

Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-09-06 06:51:02 +00:00
Kyösti Mälkki 3fd259c91d postcar: Add cbmem_stage_cache
S3 resume path executing through postcar was unable
to utilise cached ramstage in CBMEM.

Change-Id: Icc8947c701ca32b4f261ebb78dfc1215b7ed2da0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 05:02:44 +00:00
Kyösti Mälkki ef40c0ce91 AGESA: Drop LATE_CBMEM_INIT in new interface
Change-Id: Iffa6cf495b4649f73a1095732509f195ac828248
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-06 05:00:48 +00:00