The ifittool is used instead. Drop old code.
Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add the IntelFirmwareInterfaceTable-tool to modify the FIT.
As cbfstool is overloaded with arguments, introduce a new tool
to only modify FIT, which brings it's own command line syntax.
Provide clean interface to:
* Clear FIT
* Add entry to CBFS file
* Add entry to REGION
* Delete entries
* Add support for types other than 1
* Add support to dump current table
* Add support for top-swap
* Sort entries by type
Most code is reused from existing cbfstool and functionality of cbfstool
is kept. It will be removed once the make system uses only ifittool.
Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout"
and https://github.com/slimbootloader/slimbootloader .
Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.
Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.
Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.
Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).
BUG=b:126593573
TEST=Used with WIP Picasso
Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.
Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
coreboot has decided to go with 96 characters per line.
Original Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add the ability to generate two PSP directory table levels. The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.
This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.
BUG=b:126593573
TEST=Used with WIP Picasso
Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.
Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Allow the soc build to pass a soft fuse value to the utility. This
helps maintain compatibility across PSP generations.
Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.
TEST=Verify google/grunt amdfw.rom unchanged before and after.
Compare internal board using override before and after.
Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.
The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.
This results in the following example changes:
mb/google/sarien (GbE, PDR, EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-------------------------------
+BIOS r rw rw rw r
mb/google/eve: (no GbE, no PDR, no EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-ME r rw r
-GbE r rw
-EC r rw
-------------------------------
+BIOS r rw
+ME r rw
+GbE
+EC
BUG=b:134703987
Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.
Also remove all other IS_ENABLED() checks.
Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add T32 scripts that allow debug of any coreboot stage
on qcs405.
Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the following error from clang invoking gcc linker with wrong arg:
i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1
Just remove --rtlib switch from CFLAGS relating to clang
Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.
Mention this in readme as it may help someone.
Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For x64 and x86_32 configurations, apply the -march flag to both GCC and
Clang flags.
This solves the problem of Clang-compiled coreboot failing due to Clang
emitting SSE instructions for code that is executed while SSE is not
enabled.
This patch takes functionality targeted for GCC configurations and moves
it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order
that it applies to both GCC and Clang.
This is an alternate patch to CB:32887.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It is possible that 'lnode->val' is set to 0 on a previous iteration of
the loop, so check that it is non-null here before dereferencing it.
Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The 'new_type' function already allocates memory, so it is only
necessary to clone the existing type if this function is not called.
Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity Scan CID 1129106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It is possible that 'filename' is still null in this if statement,
so we add an extra check to prevent a null dereference in strcmp.
Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1395330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In each of these cases it is possible that 'member' is NULL at the
beginning, which will skip the earlier while loops entirely and cause
a NULL dereference later on. Add extra error checks to prevent this.
Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SMBus adapter will not appear if i2c-i801 module is not loaded.
Added it to the readme.
Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"
Tested on 945G-M4 board.
Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).
Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.
Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Free 'arg_type' after it is used to prevent a memory leak.
Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.
Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.
Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.
Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
'name' and 'env' are supposed to be file system paths,
but could overflow the buffer if configured incorrectly.
Let's avoid that entirely.
Found-by: Coverity Scan #1362515
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can
fail, so add appropriate error checks for those cases.
This incidentally fixes a possible memory leak when
'malloc_fo_sub' succeeds but 'remalloc_fo' does not.
Found-by: Coverity Scan #1396050
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
As the previous comment indicated, this null check is
currently superfluous, but adding it in makes Coverity
happy, and future-proofs the code in case someone changes
the internals of 'find_fcba' later and forgets/doesn't know
to update this error check.
Found-by: Coverity Scan #1395066
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Should include vb2_sha.h header when SHA library functions or
constants are required. This replaces NEED_VB2_SHA_LIBRARY.
BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.
smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)
Example:
device pci 1c.1 on
smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
end # PCIe Port #2 Integrated Wireless LAN
Tested on Lenovo T520.
Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.
This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.
Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)
Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
TEST=build & run
Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If override tree does not have any device, then the chip info
structure in it cannot be associated with the correct device and ends
up being added as a standalone chip info structure without any device
actually using it. This change prevents this condition by throwing an
error during compilation.
BUG=b:130342895
Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The last attribute was never returned.
Fix size compare to retrieve all attributes.
Manually tested and seen all attributes, including the last one.
Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Support for ACPI specification version 6.3:
Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.
Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.
PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.
SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.
MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.
MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.
New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.
PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.
NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".
HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".
GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.
iASL: Update the HMAT example template for new fields.
iASL: Add support for the new revision of the GTDT (Rev 3).
More changes in this version at https://acpica.org/node/166
Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Elyes HAOUAS