Commit Graph

3904 Commits

Author SHA1 Message Date
Stefan Reinauer 9dd27bc03a the tool chain settings should not be in renamed (as they will never live in
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 17:13:58 +00:00
Stefan Reinauer 36f230eefb whoops. missed those two..
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:54:53 +00:00
Stefan Reinauer 775c04e537 commit svn:externals for last commit (what a pain) (1/2)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:23:20 +00:00
Stefan Reinauer 0867062412 This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:17:49 +00:00
Warren Turkal 9702b6bf7e add new supported chipset
Add identification for X58 and ICH10R.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 14:11:42 +00:00
Patrick Georgi b1ff95c14d This copy of flashrom is old and unmaintained. Delete it to avoid
confusion, after we had a grace period to get people to move over to the
new repository.

History stays available for the archaeologists and for ancient
checkouts (potentially with local changes). Use "svn diff" to get local
changes, and apply it to a newer tree (if you manage to apply it, that
is).

The new repository is available at:
svn://coreboot.org/flashrom/trunk

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 22:47:06 +00:00
Stefan Reinauer 1220c50919 flashrom is a separate project now. Thus we don't enforce it on our users.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 22:40:48 +00:00
Yinghai Lu 3f57548625 Impact: fix vmlinux from 2.6.30
from 2.6.30 (?)
the new vmlinux with per_cpu and brk support will have more sections.

Elf file type is EXEC (Executable file)
Entry point 0x200000
There are 7 program headers, starting at offset 64

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000200000 0xffffffff80200000 0x0000000000200000
                 0x0000000000e46000 0x0000000000e46000  R E    200000
  LOAD           0x0000000001046000 0xffffffff81046000 0x0000000001046000
                 0x00000000001406e0 0x00000000001406e0  RWE    200000
  LOAD           0x0000000001200000 0xffffffffff600000 0x0000000001187000
                 0x0000000000000888 0x0000000000000888  RWE    200000
  LOAD           0x0000000001388000 0xffffffff81188000 0x0000000001188000
                 0x000000000008a086 0x000000000008a086  RWE    200000
  LOAD           0x0000000001600000 0x0000000000000000 0x0000000001213000
                 0x0000000000015e20 0x0000000000015e20  RWE    200000
  LOAD           0x0000000001629000 0xffffffff81229000 0x0000000001229000
                 0x0000000000000000 0x0000000000208000  RWE    200000
  NOTE           0x0000000000b3c7e8 0xffffffff80b3c7e8 0x0000000000b3c7e8
                 0x0000000000000024 0x0000000000000024         4

 Section to Segment mapping:
  Segment Sections...
   00     .text .notes __ex_table .rodata __bug_table .pci_fixup .builtin_fw __ksymtab __ksymtab_gpl __ksymtab_strings __init_rodata __param 
   01     .data .init.rodata .data.cacheline_aligned .data.read_mostly 
   02     .vsyscall_0 .vsyscall_fn .vsyscall_gtod_data .vsyscall_1 .vsyscall_2 .vgetcpu_mode .jiffies 
   03     .data.init_task .smp_locks .init.text .init.data .init.setup .initcall.init .con_initcall.init .x86_cpu_dev.init .altinstructions .altinstr_replacement .exit.text .init.ramfs 
   04     .data.percpu 
   05     .bss .brk 
   06     .notes 

So need to increase NR_SECTIONS.

also fix one typo about phys address mask.

Peter says: A similar fix was also implemented by Maciej Pijanka, so let's
commit this now, eh.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-28 15:04:06 +00:00
Uwe Hermann 3ddbfb8901 Add a target/ directory for the VIA EPIA-M700 board, so we can build it.
Note that this board is nowhere near usable, further patches will follow
and hopefully get this into buildable and usable shape.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-27 16:06:51 +00:00
François-Regis Vuillemin 22b44ba9c3 Add dump support for SMSC LPC47N252.
Signed-off-by: François-Regis Vuillemin <coreboot@miradou.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-27 02:23:26 +00:00
Uwe Hermann db52fb8024 Don't dump 0x07 registers, they're useless as they change every time
some software wants to do an LDN access (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:53:07 +00:00
Michael Gold 556e6fb2e3 This adds register definitions for all logical devices on the SMSC
LPC47U33x, allowing 'superiotool -d' to work.

Also, some consistency string fixes.

Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:25:04 +00:00
Arjan Koers 78fdd6046e Add dump information for F71862FG and F71863FG.
Signed-off-by: Arjan Koers <0h3q2rmn2bdb@list.nospam.xutrox.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-26 15:16:21 +00:00
Myles Watson bb21b2e45b Remove the object files for cbfs from target directories and add a
cbfstool-clean target to the Makefile.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-25 21:44:38 +00:00
Myles Watson 455e223365 The problem is that the check to see if we're at the end is never reached. I
didn't look into it enough to know why fssize is 32 bytes larger than the
offset.  There may be another bug here.  Maybe something with the CBFS header
not being included or excluded from the calculation?

Anyway, this patch fixes it for all cases size > 32.

I also changed the error message so that it doesn't look like the ROM is full
just because it can't find room for a file.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-25 15:54:57 +00:00
Uwe Hermann 8c19f949fe Add support for the Soyo SY-6BA+ III board.
Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots
Linux fine. Detailed status at:

  http://www.coreboot.org/Soyo_SY-6BA_Plus_III

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro@ziltro.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-24 00:35:07 +00:00
Rudolf Marek 3310d75e6c This patch adds a proper namestring generation to our ACPIgen generator.
Its used for Name and Scope and Processor now. As bonus, it allows to
create a multi name paths too. Like Scope(\ALL.YOUR.BASE).

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-21 20:26:13 +00:00
Myles Watson f17f647a62 Undo my ugly commit that added uses clauses in lots of places instead of one.
Fix configuration of all boards. (Abuild tested)
Hopefully fix compilation of PPC boards (they've never compiled for me.)

Apologize profusely.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 21:18:14 +00:00
Stefan Reinauer 24fbb7d66f work around initobject breakage in pc80/Config.lb
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 19:50:58 +00:00
Uwe Hermann 6114311c8e Convert the MSI MS-6178 board to CBFS.
Also, enable HIGH_TABLES support for this board.

The HIGH_TABLES failed with:

  No matching ram area found for range:
    [0x00000000000f0000, 0x0000000000100000)
  Ram areas
    [0x0000000000000000, 0x0000000000001000) Reserved
    [0x0000000000001000, 0x00000000000a0000) RAM
    [0x0000000000100000, 0x000000000fff0000) RAM
    [0x000000000fff0000, 0x0000000010000000) Reserved
  SELFBOOT RETURNED!
  Boot failed.

The fix was to change northbridge.c as follows:

  - ram_resource(dev, idx++, 1024, tolmk - 1024);
  + ram_resource(dev, idx++, 768, tolmk - 768);

This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 15:41:49 +00:00
Harald Gutmann 62cfe169fa ChangeLog:
Add initial ACPI support for M57SLI.
	Activates/Enables:
		* native Coreboot ACPI for M57SLI
		* Soft-Power-Off
		* PowerNow!
		* High Precision Event Timer
		* Windows booting with ACPI support

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 12:03:40 +00:00
Ward Vandewege ecf4ef0b26 Make sure the address variable is initialized to zero - it is only set when a
[base address] parameter is supplied on the command line... This patch fixes
random segfaults when using 'cbfstool add'.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 16:38:35 +00:00
Harald Gutmann da8336176e Change Log:
Fix interrupt handling in mptable.c on M57SLI.

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 10:05:41 +00:00
Harald Gutmann b735f85379 Change Log:
Activate HIGH_TABES on M57SLI

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-18 09:46:11 +00:00
Myles Watson 82bc9bc31e Fix configuration of boards that didn't have uses CONFIG_USE_INIT. Trivial.
Abuild tested with -C.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17 16:38:43 +00:00
Marc Jones aac8dc81c5 Patch AMD Fam10 C2 for errata 327, 344, 346, 354, 351.
Removed c2 HT Phy 520a/530a reserved bit.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-17 15:33:57 +00:00
Marc Jones cbefc238c5 Maximilian Thuermer found a bug where the HT link capability code was always
updating the passed value to the next link offset even when it was on the
requested link (cap_count).

Maximilian also found a bug where the linktype was still getting attributes
even when it wasn't initialized.

This should fix the HT problems for Fam10 C2. There are still issues with the
microcode which need to be resolved.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16 23:02:39 +00:00
Ronald G. minnich d41de2ea7a These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice 
thing: no more included .S or .c files. It's all separate compilation. 
That should allow our Makefiles to work much better.

Note that the current non-CAR implementation is the default and 
continues to work (tested FILO boot to Linux on both CAR and non-CAR).

Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that 
depend on this variable are grouped in one if, and the other parts 
(romcc etc.) are in the else. This change is a model of how we should be 
able to do other motherboards.

Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options. 

Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file. 

Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3. 

Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem. 

Index: src/pc80/serial.c
make uart_init non-static. 

Index: src/pc80/Config.lb
add initobject

Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3. 

Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init. 

Index: src/arch/i386/init/car.S
generic i386 car code from v3. 

Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section. 

Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well 
get all the debugging we can. 

Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds. 

Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-16 15:02:52 +00:00
Ioannis Barkas 3ba18a67eb Fix typo in Winbond W83977TF register listing.
Signed-off-by: Ioannis Barkas <tripl3fault@yahoo.com>
Signed-off-by: Nikos Barkas <levelwol@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-12 14:20:27 +00:00
Myles Watson 124d8767da Fix s2895 failover booting.
Abuild tested and boot tested on s2895 and serengeti_cheetah.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-11 18:27:41 +00:00
Stefan Reinauer 9ca6ed548e this port is horribly broken and should not have been checked in. This patch
gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-09 15:22:47 +00:00
Ronald G. Minnich a88db7bb87 Fix a little white space issue. Also, don't copy the rom image
if it is already in its correct location. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
   
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-09 14:44:37 +00:00
Uwe Hermann e8c6f86b80 Add (commented) line for VGA blob adding (CBFS version) to simplify things for users a bit.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-08 13:05:47 +00:00
Ronald G. Minnich 6ce41c06cc This is transition code for cbfs to implement
cbfs files at fixed addresses.

I call this transitional as the approach I am taking is to add
capability to cbfstool but not change code in a way that will break
existing usages. Later, once we're sure nothing has broken, we can start to 
smooth the edges. 

Right now, fixed address file are only supported via the add command. 

There is one additional command syntax, so, example:
cbfstool add rom romstrap optionrom 0xffffd000

Will add the file to that fix location for a romstrap.

The assumption is that the ROM is based at the end of a 32-bit address
space. As you can see from the code, that assumption can easily be
over-ridden, if we ever need to, with a command option.

Here is one example output result.

rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print
x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0
Alignment: 16 bytes

Name                           Offset     Type         Size
h                              0x0        optionrom   251
                             0x130      free         917120
h3                             0xdffe0    optionrom    251
                             0xe0110    free         97960

The way this is implemented is pretty simple. I introduce a new
operator, split, that splits an unallocated area into two unallocated
areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits:
0 split -- the free area is the exact fit
1 splits -- need to split some off the front or back
2 splits -- need to split off BOTH the front and back

I think you'll be able to see what I've done. I call this transitional
because, in the end state, we only need one allocate function; for now
I've left two in, to make sure I don't break compatibilty.

Why I like this better than ldscript approach: I like having the
ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes
romstrap visible as a first class object. I think I would have latched
onto a problem I was having much more quickly had I remembered the
ROMSTRAP. It gets lost in the linker scripts.

At this point, we should be able to start removing special ROMSTRAP location 
code from linker scripts. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-08 03:33:57 +00:00
Uwe Hermann d64f403f8e A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes:
- Make get_dsdt script executable.

 - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.

 - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
   is correct.

 - Fix broken or incorrect #include names to increase likelyhood of a
   successful compile.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-07 14:38:32 +00:00
Uwe Hermann 0ffff3434e First bunch of coding style and consistency cleanups for the
EPIA-M700 target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-07 13:46:50 +00:00
Carl-Daniel Hailfinger cff071ab0e When I started refactoring mainboard Config.lb, I added two different
files for targets without failover:
src/config/nofailovercalculation.lb (64 kB XIP)
src/config/nofailovercalculation128.lb (128 kB XIP)
Targets with other XIP sizes were ignored.

This patch moves XIP size back into mainboard code.

Benefits from this patch:
- src/config/nofailovercalculation128.lb is no longer needed
- Targets with XIP sizes besides 64k and 128k benefit from refactoring
- Conceptually, this makes the include files pure calculation files
without settings.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 16:50:38 +00:00
Patrick Georgi a7d8ae3b1d Make failover larger and decrease fallback's size so the total stays the
same. The errata need some extra room in failover.

Trivial and abuild tested


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 12:19:59 +00:00
Marco Schmidt a774192e22 Fix for Erratum 350 for AMD Fam10h CPUs.
Compared to posted patch, there are whitespace fixes
(request by Uwe), and a guard to run the erratum only
on AMD_RB_C2 (request by Marc).

Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 11:33:58 +00:00
Marco Schmidt c263b4471d Fix for Erratum 343 for AMD Fam10h CPUs.
Signed-off-by: Marco Schmidt <mashpb@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 11:21:52 +00:00
Patrick Georgi 240ef7c769 Change the CBFS build process to use coreboot.rom
instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.

This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.

Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
  crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
  as it's done everywhere else
- change the default config of abuild to not
  provide ROM_IMAGE_SIZE values for the images
  in a CBFS configuration
- change abuild's crosscompile autodetection to
  not try to use "i386-elf-i386-elf-gcc" (which
  is bogus)

Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS

The changes in util/abuild/abuild are trivial and
abuild tested.

As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-06 07:19:53 +00:00
Carl-Daniel Hailfinger aa58f5427f Fix non-revF K8 ram init compilation which was broken in r4341.
Change all printk_raminit to printk_spew.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 23:43:11 +00:00
Uwe Hermann 20a98c9201 Initial untested board code for the VIA EPIA-M700 Mini-ITX board.
The patch has been submitted by bari <bari@onelabs.com> and written
by OLPC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 23:02:43 +00:00
Carl-Daniel Hailfinger 3c45a96138 K8 RAM init debug messages are pretty short and sometimes cryptic. Make
them a bit more verbose and hopefully more understandable.

Old messages for my machine with 5 GB:
RAM: 0x00400000 kB
Ram3
[...]
Initializing memory:  done
RAM: 0x00500000 kB

New messages:
RAM end at 0x00400000 kB
Adjusting lower RAM end
Lower RAM end at 0x003f0000 kB
Ram3
[...]
Initializing memory:  done
Handling memory hole at 0x00300000 (default)
RAM end at 0x00500000 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x00500000 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x00300000 kB

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 20:37:35 +00:00
Carl-Daniel Hailfinger 87e7050bff die() does never return. Annotate it as such.
Any endless loop after die() can be eliminated.
Dereferencing a NULL pointer is bad. die() instead.
Replace endless loops with die().

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 11:41:51 +00:00
Zheng Bao 28d71b9445 After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.

Tested on dbm690t.

Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.

http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 10:00:07 +00:00
Elia Yehuda a24e1dd6da Add a hopefully more correct and flexible set_dram_buffer_strength()
function based on test results with many different DIMMs.

Tested by Uwe Hermann <uwe@hermann-uwe.de> on hardware.

Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see.

Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 00:22:25 +00:00
Myles Watson 1725703a1d The point of the patch is to make it easier to understand the raminit
code, specifically the difference between pre_f and f code.

The only functional changes are in printk statements.  The rest is white space.

1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks.  All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code

There is much more that could be done, but it's a start.

Abuild tested and boot tested on s2892 and serengeti_cheetah.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-04 20:18:42 +00:00
Zheng Bao d11bd003c6 This patch is about some noticable bugs which was made by no reason.
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
  (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
      In rpr 5.10.2, step 2, step 2.1 & step 2.6
  (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
      instead of PCIEIND_P: 0x20.
      In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-04 01:57:03 +00:00
Luc Verhaegen a9c5ea08d0 Revert "CMOS: Add set_option and rework get_option."
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.

Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 14:19:33 +00:00