Commit graph

14735 commits

Author SHA1 Message Date
Frank Wu
35bcf5071c mb/google/zork/var/vilboz: Generate new SPD ID for new memory parts
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Hynix H5ANAG6NCJR-XNC
2. Micron MT40A512M16TB-062E:R
3. ADATA 4JQA-0622AD

BUG=b:199469240
BRANCH=firmware-zork-13434.B
TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-02 08:12:22 +00:00
Angel Pons
8d5b674739 soc/intel/braswell: Set GNVS DPTE via devicetree
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS
field, as newer Intel platforms do.

Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01 16:02:13 +00:00
Zhi Li
af207a5279 mb/google/dedede/var/storo: Add fw_config probe for multi audio codec
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"

BUG=b:202463494
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally

Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01 15:58:31 +00:00
Dan Callaghan
4e6c915fcc mb/google/brya/var/brya0: add HPS as generic I2C peripheral
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than
a user-facing camera.

Because HPS uses I2C address 0x51, which may conflict with the
user-facing camera EEPROM, introduce a new fw_config bit to indicate
whether HPS is present.

BUG=b:202784200
TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage
TEST=ectool cbi set 6 0x28191 4  # set bit 17 for HPS
TEST=flashrom -p internal -w image-brya0.serial.bin

Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01 15:58:25 +00:00
David Wu
cbcc361def mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for brask
Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask.

BUG=b:197385770
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01 15:53:36 +00:00
Joey Peng
b0c1e73928 mb/google/brya/var/taeko: Add probe for MAX98357+ALC5682I_VS
Add probe function for the "VS" version of the audio amplifier so taeko
can recgonize MAX98357 with ALC5682I_VS.

BUG=b:202913837
TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize
MAX98357 with ALC5682I_VS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2021-11-01 15:47:43 +00:00
RobertChen
f6c29165b2 mb/google/dedede/var/kracko: Add Wifi SAR for kracko
Add wifi sar for kracko

BUG=b:194460420
TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage

Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-11-01 10:29:23 +00:00
Alan Huang
5355436990 mb/google/brya/var/brask: Correct the GPIO config of buzzer
GPP_B14 is used by buzzer and should be set to NF1 'SPKR'.

BUG=b:198998974
TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps.

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29 18:31:54 +00:00
Wisley Chen
550bdc9050 mb/google/brya/anahera: Disable autonomous GPIO power management
With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.

BUG=b:202246591
TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage.

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29 17:10:33 +00:00
David Wu
287cc02c00 mb/google/brya/var/kano: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:201266532
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29 16:53:14 +00:00
Angel Pons
9c30a2944b mb/prodrive/hermes: Enable LTR for all PCIe ports
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH
PCIe root ports.

TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv`

Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29 15:01:13 +00:00
Angel Pons
047835aba7 mb/prodrive/hermes: Map PCIe clocks to root ports
Map each PCIe clock source to the corresponding root port. Also, correct
the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin.
The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0.

TEST=Check that Linux sees the same PCIe devices with this commit:

 - All 5 onboard Ethernet NICs
 - BMC
 - Two random graphics cards in PEG0 and PEG1 slots
 - M.2 M NVMe SSD

Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29 15:00:55 +00:00
Angel Pons
1bfabb0bc0 mb/prodrive/hermes: Fix PCIe ClkSrc configuration
Correct the PCIe clock source configuration as per the schematics.
Apparently, FSP does not turn off unused PCIe clock sources when using
SPS (Server Platform Services) firmware, but it does when using CSME
firmware.

TEST=BMC and Ethernet NICs get detected when using CSME firmware.

Change-Id: Id25a34816f512510640db95251a7a792c1eebe62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29 14:11:53 +00:00
Bernardo Perez Priego
e008c469c3 Revert "mb/intel/adlrvp: Remove EC region"
This reverts commit 0a1602217f.

EC region is required in order to provide unified coreboot image for
Chrome and Windows SKU RVP's. Also removing EC region causes a regression
for ADL-P platforms.

With this patch EC region is included back into flash map.

Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-10-29 00:53:56 +00:00
David Wu
eea22f60d2 mb/google/brya/var/kano: Add fw_config probe for MIPI camera
Add fw_config probe for MIPI OVTI2740 camera

BUG=b:194926283
TEST=FW_NAME=kano emerge-brya coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic5a7cebf1f5c847c01e951a237af691e0ad6c73d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29 00:53:19 +00:00
Dan Callaghan
b00bfd0765 mb/google/brya/var/taeko: add HPS as generic I2C peripheral
BUG=b:202784200
TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage

Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I400719d762b001811f809f9549fd030dff9928d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-28 23:11:55 +00:00
Arthur Heymans
59a348b75a drivers/net/r8168.c: Guard against generating power resource
Not all platforms need to generate power resources, but the code does
not get optimized out at build time because the devicetree gets
compiled into a linked list. As this code pulls in some heavy ACPI
dependencies that is even implemented with weak empty function it
makes sense to optimize out this code using a Kconfig constant.

This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l.

Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-28 17:39:37 +00:00
Kevin Chiu
ea9425504f mb/google/guybrush/var/nipperkin: update telemetry settings
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC
scale/offset value, it needs to update the two load line slope
settings for the telemetry.

AGESA sends these values to the SMU, which accepts them as units of
current. Proper calibration is determined by the AMD SDLE tool and the
Stardust test.

VDD scale: 92165 -> 73457
VDD offset: 412 -> 291
SOC scale: 30233 -> 30761
SOC offset: 457 -> 834

BUG=b:200194315
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     pass AMD SDLE/Stardust test

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: If53c173000a276a80247ccb08736280a25948939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-28 17:37:11 +00:00
Rob Barnes
9a56ff9c2d mb/google/guybrush: Move EN_PWR_FP from GPIO_32 to GPIO_3
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32
for other uses.

This move applies to all board except:
* Guybrush
* Nipperkin board version 1

Add callbacks for variants to override fpmcu shtudown gpio table and
fpmcu disable gpio table.

BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint
still works.

Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27 23:23:05 +00:00
Karthikeyan Ramasubramanian
b4182989d7 mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1

Update the GPIO configuration, device tree configuration accordingly.

BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27 23:22:53 +00:00
Karthikeyan Ramasubramanian
d3c565e745 mb/google/guybrush: Fix GPIO overrides during verstage
GPIO overrides are defined for verstage. But the overrides are neither
enabled nor applied during verstage. Enable the overrides and apply them
during verstage.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and
cold reboot cycling for 10 iterations each. Ensure that all the PCIe
devices are enumerated fine.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-27 23:22:38 +00:00
Mark Hsieh
a1b299cd69 mb/google/brya/var/gimble: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:200918380
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27 22:17:29 +00:00
Wisley Chen
8cc0a91c3c mb/google/dedede/var/lantis: Generate new SPD ID for new memory parts
Add new memory parts in memory_parts_used.txt  and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL

BUG=b:204015941
TEST=run part_id_gen to generate SPD id

Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
2021-10-27 22:17:04 +00:00
Frank Wu
c299a6a33c mb/google/dedede/var/driblee: Generate new SPD ID for new memory parts
Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. H54G46CYRBX267

BUG=b:204023388
BRANCH=firmware-keeby-14119.B
TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27 22:17:00 +00:00
Karthikeyan Ramasubramanian
30c441fc2d mb/google/guybrush: Remove WWAN_DISABLE GPIO
In-band controls work to enable/disable the WWAN module. Hence
WWAN_DISABLE_GPIO is not critical and can be marked as not connected.

BUG=b:188415287
TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is
enumerated on boot and reboot.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-10-27 22:03:56 +00:00
Karthikeyan Ramasubramanian
750abb1fe7 mb/google/guybrush: Update SD_AUX_RESET_L signal
On all upcoming variants and board versions of existing variants,
SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all
boards except:
* All board versions of Guybrush
* Nipperkin Board Version 1.

Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18.
Configure the gpios accordingly in baseboard, guybrush and nipperkin
variants accordingly. Also update the DXIO port descriptor for SD PCIe
engine with the corresponding AUX reset GPIO.

BUG=b:202992077
TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD
Controller and SD Card are enumerated fine. Ensure that the enumeration
is successful after a suspend/resume cycle.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27 22:03:42 +00:00
David Wu
1bdf09d91a mb/google/brya/var/kano: Disable unused PCIE root port in devicetree
The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use
these. Having them enabled will occasionally cause suspend
attempts to fail, therefore disable them in the overridetree.

BUG=b:203389490 b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27 22:01:03 +00:00
Karthikeyan Ramasubramanian
d125566582 mb/google/guybrush: Reconfigure GPIO_5
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On
Nipperkin board version 1, pen is not stuffed and instead the GPIO is
used to control LCD Privacy settings. On upcoming Nipperkin board
versions and other variants, GPIO_5 is not used. Configure GPIO_5
accordingly.

BUG=b:202992077
TEST=Build and boot to OS in Guybrush. Ensure that the configuration is
retained on existing boards.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27 21:59:37 +00:00
Angel Pons
d687d8dc68 mb/siemens/chili: Drop redundant Kconfig select
The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through
the `SECUNET_DMI` option. So, there's no need to select both of them.

Change-Id: I784df87893043a011906af8808aff27d636c7626
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-27 15:04:26 +00:00
Wisley Chen
41e8e8aacc mb/google/dedede/var/drawcia: Generate new SPD ID for new memory parts
Add new memory parts in memory_parts_used.txt  and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL

BUG=b:204014463
TEST=run part_id_gen to generate SPD id

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27 14:07:28 +00:00
Wisley Chen
99165592c4 mb/google/dedede/var/haboki: Generate new SPD ID for new memory parts
Add new memory parts in memory_parts_used.txt  and generate SPD id for
these parts:
Micron MT53E512M32D1NP-046 WT:B
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL

BUG=b:204015944
TEST=run part_id_gen to generate SPD id

Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27 14:07:16 +00:00
David Wu
ba6fdc892d mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).

BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27 14:07:01 +00:00
David Wu
008c2b18b1 mb/google/brya/var/kano: Update the FIVR configurations
This patch set disables the external voltage rails since kano
board doesn't have V1p05 and Vnn bypass rails implemented.

BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-27 14:06:45 +00:00
Kevin Chiu
64d39f98e8 mb/google/guybrush/var/nipperkin: config eSPI alert as in-band
To prevent unexpected alert from eSPI to SOC, configure this alert pin
to in-band.

BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-10-27 14:06:26 +00:00
Kevin Chiu
f473af7f00 mb/google/guybrush/var/nipperkin: Add G2 GTCH7503 HID TS support
Follow up the G2 spec: G7500_Datasheet_Ver.1.2

BUG=b:203607764,b:202090378
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     TS is functional

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I98dd3095043ab537d91e81b84944779240b203ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-27 14:05:48 +00:00
Furquan Shaikh
d06c09179a intel/adlrvp: Add sub-regions to SI_ME in chromeos.fmd
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.

BUG=b:189177538

Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-26 23:22:00 +00:00
Yongkun Yu
5c78ff9b4a mb/google/dedede/var/blipper: Add fw_config probe for multi audio codec
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"

BUG=b:197694580
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally

Signed-off-by: Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
Change-Id: I422f206b8f1f3705a65808041f1a1544c461b431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-26 20:00:06 +00:00
Angel Pons
0515aa1978 mb/prodrive/hermes: Remove overridetree
There's no need to have an overridetree with a single board variant.

TEST=Compare static.c and observe only device order has changed.

Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26 16:16:01 +00:00
Angel Pons
57f09803bb mb/prodrive/hermes: Reorganize per-port PCIe settings
Move per-port PCIe settings inside the corresponding PCIe root port
device. Also, remove several unnecessary and/or redundant comments.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-26 16:15:50 +00:00
Kevin Chiu
1a950d6466 mb/google/guybrush/var/nipperkin: override dxio to turn off WLAN ASPM L1.2/L1.2
turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure.

BUG=b:198258604
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     AP is able to be probed by wlan module

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-25 21:45:11 +00:00
Mac Chiang
299649a31c mb/google/brya/variants/gimble: Enable Bluetooth offload support
Enable CnviBtAudioOffload UPD

BUG=b:199180746
TEST=emerge-byra coreboot

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-25 14:23:20 +00:00
Kyösti Mälkki
aed59b6721 AGESA binaryPI: Use common acpi_fill_madt()
Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-22 14:28:27 +00:00
Kyösti Mälkki
c25ecb5443 arch/x86/ioapic: Select IOAPIC with SMP
For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.

Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 14:18:45 +00:00
Kyösti Mälkki
4bab5691cc mb/emulation/qemu-i440fx: Select IOAPIC
For SMP operation IOAPIC needs to be configured.

For a build with MAX_CPUS=1 emulation might still decode
the IOAPIC MMIO window, it does not really matter to have
it always reserved.

Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-22 14:18:24 +00:00
Felix Held
4dd7d11965 cpu/x86/mp_init: move printing of failure message into mp_init_with_smm
Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.

Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22 01:27:07 +00:00
Felix Held
d27ef5bf6f cpu/x86/mp_init: use cb_err as mp_init_with_smm return type
Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:51:43 +00:00
David Wu
91e8c2a1d4 mb/google/brya/var/kano: Correct GPIO GPP_R6 and GPP_R7 setting
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).

BUG=b:202913826
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:05:51 +00:00
David Wu
e2c6d9c7cb mb/google/brya/var/brask: Correct SSD power sequence
M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-21 20:05:34 +00:00
Kevin Chiu
48bd857789 mb/google/guybrush/var/nipperkin: Enable GPP2 for NVMe bridge eMMC storage
BUG=b:195269555
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     eMMC sku is bootable

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: If9e0fdc1667cbaac05fdf4c6689d47a561016c9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-21 20:04:59 +00:00
Karthikeyan Ramasubramanian
679f4fa465 mb/google/guybrush/var/nipperkin: Override GPIO configuration
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected
in nipperkin. Override those GPIO configurations.

BUG=None
TEST=Build and boot to OS in Nipperkin.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-21 19:59:57 +00:00