Commit Graph

31415 Commits

Author SHA1 Message Date
Arthur Heymans d3c58fdc64 soc/qualcomm: Link cbmem.c only in romstage
Change-Id: I008fcca024fecf462c4b550b8dedbf4b06e491b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36368
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 20:58:43 +00:00
Julius Werner 211792feab rockchip/rk3288: Split free SRAM more evenly between stages
When CB:33068 disabled the bootblock console on RK3288, it saved a
whooping 7K of SRAM, but it didn't readjust the stage boundaries to
spread that bounty evenly. This patch moves 4K of free space from the
bootblock to verstage/romstage to allow for future expansion.

Change-Id: I68a09ba80bde0d4f17fba1f7b38c63b7cf2a4672
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14 17:10:13 +00:00
Wim Vervoorn dd0dc1ac92 security/intel: Hide Intel submenu when INTEL TXT is disabled
An empty submenu Intel is displayed in security menu when INTEL_TXT is
disabled.
Enable submenu Intel only when INTEL_TXT is enabled.

BUG=N/A
TEST=build

Change-Id: Iff1d84ff60a15259b60c6205a63a27ecb26346a3
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-14 16:00:45 +00:00
Xiang Wang d577726460 soc/sifive/fu540: Support booting from SD card
Change-Id: I18948d31c0bf0bf9d641480a35fc710b9ee8ae84
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-14 11:38:43 +00:00
Xiang Wang b134945ec1 drivers/spi: add drivers for sdcard mounted on the spi bus
Currently supports initialization, read, write, and erase operations.
Tested on HiFive Uneashed

implementation follows SD association's SPI access protocol, found
as doc http://t.cn/AiB8quFZ

Change-Id: I464d2334b8227e448c1c7e324c0455023cffb72a
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14 11:38:38 +00:00
Wim Vervoorn b23f392766 vendorcode/amd/agesa: Correct typo
Correct typo of 'uninitialized'

BUG=N/A
TEST=build

Change-Id: I43c6eb0287d23546a2abb330c7cc8585a33b27b5
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36776
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:34:10 +00:00
Frans Hendriks 50b999feb8 {drivers,mainboard}: Move FSP logo support to fsp1_1
Support to display a logo using FSP 1.1 currently resides in facebook fbg1701
mainboard.

The related support is moved to drivers/intel/fsp1_1 and used by the
Facebook fbg1701 mainboard. The storage for the uncompressed logo
is changed. We don't use .bss any longer as the logo doesn't need to be
available at runtime.

BUG=N/A
TEST=booting Facebook fbg1701

Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-14 11:33:46 +00:00
Joel Kitching 348002c305 Update vboot submodule to upstream master
Updating from commit id b2c8984d:
2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM)

to commit id 87276ffe:
2019-11-07 17:46:09 +0800 - (futility: updater: Clean up hard-coded section names to preserve)

This brings in 48 new commits.

Change-Id: Iabaadc63227b856d0a2b7f3b23fe8c41b28d8eae
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-14 11:31:54 +00:00
Arthur Heymans a1928cfa28 sb/intel/i82801gx: Don't setup CIR when the northbridge is x4x
The northbridge code to set up DMI is not correct and the CIR bits
relate to that.

This fixes a regression caused by 2437fe9 'sb/intel/i82801gx: Move CIR
init to a common place', where payloads hang on southbridge IO.

Change-Id: Iabb54d9954d442a1a7b48a6c6e76faa8079a4c71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:30:43 +00:00
Arthur Heymans 2452afbe04 mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved
after console init.

Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:30:34 +00:00
Arthur Heymans aa990e9289 sb/intel/i82801jx: Move early sb init to a common place
Setting southbridge GPIO is now done after console init,
which should be fine. This code is partially copied from
i82801ix.

Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:30:21 +00:00
Arthur Heymans 399b6c11ef sb/intel/i82801gx: Add common early code
Remove some of the code duplication on i82801gx.
x4x boards are left untouched for now since that northbridge
also supports i82801jx.

The order of some things has changed:
- on i945 early_ich7_init is now done before the raminit
- enabling the IOAPIC is done before the raminit

Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:30:09 +00:00
Wisley Chen 949ff57bca /mb/google/hatch: clean manufacturing information in spd
Clean the vendor/manufacturing information in 16G_3200_4bg spd to
become generic spd.

BUG=None
TEST=emerge-hatch coreboot

Change-Id: I163dc4631a6b71efd36c75cfe1fc759040113387
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36810
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:29:27 +00:00
Wisley Chen 571b14ef23 /mb/google/hatch/var/dratini: Add new memory support
1. ram id 8: 16G 2666 2 bank groups memory
2. ram id 9: 16G 3200 4 bank groups memory

BUG=b:142762387
TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC)

Change-Id: Ic63d911458b59de11c12ce776f6f7d04b1eb3b6c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36667
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 11:29:11 +00:00
Subrata Banik ae695757f4 soc/intel/tigerlake: Include few more Tigerlake device IDs
This patch performs below operations
1. Add few more MCH, ESPI and IGD IDs
2. Remove TGL-H IDs
3. Rename existing as per applicable names
4. Remove TODO from report_platform.c file
5. Include TGL IDs into report_platform.c file

Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-14 11:29:03 +00:00
Arthur Heymans 10c8ad8d78 nb/intel/i440bx: Remove unnecessary __SIMPLE_DEVICE__
This file is only included in romstage.

Change-Id: Ib9ee6e88e7a6ef81034de608232a05e92a16d5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-14 11:28:27 +00:00
Selma BENSAID 6aa81fa55e Fix sarien depthcharge make build
CONFIG_MAINBOARD_DEPTHCHARGE is set to "" for
boards not configuring it.

Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: If61a1371ad8baf165b09ce045fc1a6c205c2c0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-14 11:08:19 +00:00
Julius Werner 32e13c0b00 cbfs: Stop checking master header
The CBFS master header is a legacy structure that just conveys the same
information we already have from the FMAP these days. We're still
including it to support older CBFS implementations in some payloads, but
there's no need for coreboot itself to follow this indirection anymore.
This patch simplifies the default CBFS locator to just return the CBFS
offset and size from the FMAP directly.

Change-Id: I6b00dd7f276364d62fa1f637efbaee0e80607c49
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36688
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 03:31:17 +00:00
Julius Werner cefe89ee79 lib/fmap: Add optional pre-RAM cache
This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.

In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.

Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).

Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2019-11-14 03:30:11 +00:00
Julius Werner 6abbd5b0ac cbfs: Make cbfs_master_header_props() externally available
This patch makes the CBFS default locator .locate() callback externally
available so that code which overrides cbfs_master_header_locator can
reuse or wrap it and doesn't have to copy&paste the whole thing. Use it
for the Eltan vendorcode implementation which previously did this.

Change-Id: I54dad5c8ea64ea0fc472217e275daa815736991e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36797
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14 03:30:03 +00:00
Kyösti Mälkki 44da9e73c7 sb/intel/i82801gx,ix,jx: Move HAVE_SMI_HANDLER conditional
Make these more consistent with later platforms. Followups will
do a more complete refactoring of set_acpi_mode() implementations.

Change-Id: I6a05b7600ebdc49915157eaff229459a1eea754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-13 21:15:13 +00:00
Kyösti Mälkki cd0b67b30a sb/intel/i82801dx,ix: Replace SMM_ASEG conditional
PARALLEL_MP path also calls smm_lock().

Change-Id: I270fc8266d118cd1e7245ea70b707a03aedac209
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-13 21:13:39 +00:00
Kyösti Mälkki 7630803b85 sb/intel: Remove ENABLE_ACPI_MODE_IN_COREBOOT
Change-Id: Ic807f4b4fc26232301f81c8076daf31fe58f217b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-13 21:10:08 +00:00
Andrey Petrov a7fb23081c arch/x86: Correctly determine number of enabled cores
Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN
which is correct.

TEST=tested with dmidecode

Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-13 19:11:39 +00:00
Julius Werner a2d123ea98 nvidia/tegra210: Enable RETURN_FROM_VERSTAGE to free up space
All stages on this board are very close to the limit, so enable
RETURN_FROM_VERSTAGE so that we can overlap verstage and romstage to
use the available SRAM more effectively. (Coincidentally, this also
reduces verstage size quite a bit... maybe we should consider just
making this the default at some point, there are really no downsides.)

Change-Id: I2b91fd13d147f964bcbd7b2850f8a0931ea060df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-13 09:39:27 +00:00
Arthur Heymans 87074f9042 sb/intel/i82801jx: Enable upper 128bytes of CMOS
The normal romcc bootblock uses this.

Change-Id: I60f735f703a9208911f5cc8a81930535e574644d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13 09:22:50 +00:00
Arthur Heymans dc972e17c7 nb/intel/x4x.h: Include stdint.h
The structs and function definition in that header require it.

Change-Id: I3466ff1a28459d0285e27d368314faf747e2eac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-13 09:15:59 +00:00
Arthur Heymans b236352281 sb/intel/i82801gx: Add a function to set up BAR
This removes some of the sb code in the nb.

Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-13 09:14:20 +00:00
Peichao Wang 0d92271d2c spi: Add Winbond W25Q128JW_DTR SPI ROM support
BUG=b:144297264
TEST=Boot with W25Q128JW_DTR and check MRC data save/restore works.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ica6344556e5de94555b95dd7c6df5600614811e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-11-13 09:13:25 +00:00
Kyösti Mälkki ead8a07cee intel/82801dx,ix: Rename SMM_ASEG functions
Static declarations for use with SMM_ASEG conflict those
declared globally for use with SMM_TSEG.

Change-Id: I8d2984cd8fe6208417b2eda0c10da8fc7bb76cf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35892
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13 09:12:10 +00:00
Kane Chen 799184397a mb/google/hatch/variants/helios: Fix leakage voltage problem on touchscreen
Set GPP_C4 default to low to fix leakage voltage problem on touchscreen during power on.

BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie9197192c9d6dfb30c10559990c6010b1b2d3a45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-13 05:02:33 +00:00
Wim Vervoorn 87c52809b2 lib/bootmem: Correct error message
bootmem_allocate_buffer() displayed "unitialized", this is changed to
"uninitialized".

BUG=N/A
TEST=build

Change-Id: I84ae689ddb24f3e3d2387735faf3850e6bd6dfa9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-12 18:29:16 +00:00
Arthur Heymans c6872f5524 soc/intel/tigerlake: Remove FSP-T option in Kconfig
This code lacks the temp_ram_init_params sybols so the FSP-T option
so it would fail to build.

Change-Id: Ie7d75943d89a964d0189f921fc433e4b9adfb0c5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2019-11-12 18:28:52 +00:00
Arthur Heymans b6768370d1 soc/intel/icelake: Remove FSP-T option in Kconfig
This code lacks the temp_ram_init_params sybols so the FSP-T option
fails to build.

Change-Id: I2b6278bd64a3579ed3460af39ea244c7dfd51da4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2019-11-12 18:28:45 +00:00
Alexis Savery cd3c3167df mainboard/google/hatch: Create helios_diskswap variant
Created helios_diskswap as a variant of helios (hatch variant).

BUG=b:143378037
BRANCH=None
TEST=none

Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177
Signed-off-by: Alexis Savery <asavery@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-12 18:28:07 +00:00
Arthur Heymans df9cdcfc38 arch/x86/car.ld: Rename suffix _start/_end
This is more in line with how linker symbol for regions are defined.

Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-12 18:25:42 +00:00
Wisley Chen fee2fdecc2 /mb/google/hatch: add new memory config support
1. Add 16G 2666 2 bank group
2. Add 16G 3200 4 bank group

BUG=b:142762387
TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC)

Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-11-12 18:25:14 +00:00
Uwe Poeche 996588521a src/mainboard/siemens: Use PTN3460 chip driver
This patch replaces and cleans up the redundant PTN3460 driver files in
/mainboard/siemens directories by using the now available driver in
src/drivers/i2c/ptn3460 and providing mainboard specific functions to
the driver.

TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).

Change-Id: I976a502e7176a356bab772758250db3cdff529b9
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12 18:24:31 +00:00
Uwe Poeche 11a34ec4c2 drivers/i2c/ptn3460: Provide chip driver for PTN3460
This patch provides a chip driver for the DP-2-LVDS bridge PTN3460.
The bridge is configured via I2C. As the mainboard has all the
information regarding the attached LCD type, there are three hooks into
mainboard code to get the information like EDID data and PTN config.

TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).

Change-Id: Ie4c8176cd16836fa5b8fd2f72faf7a55723b82f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-11-12 18:24:19 +00:00
Arthur Heymans c484da1a98 sb/intel/i82801jx: Add common code for LPC decode
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-12 18:23:07 +00:00
Arthur Heymans fecf77770b sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.

Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-12 18:22:57 +00:00
Bill XIE 675cb9152e util/autoport: Stop generate empty h8_mainboard_init_dock().
CB:36385 makes dock init in ramstage fully mainboard-specific, so
keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes
unnecessary and problematic.

Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-12 18:22:34 +00:00
Werner Zeh 8088584b37 payloads/external/GRUB2: Check for existing grub2 directory
When 'make clean' is executed and there is no source code cloned for
GRUB2 in payloads/external/GRUB2/grub2 (so GRUB2 has never been used on
this tree) an error message is thrown:
"fatal: cannot change to 'grub2': No such file or directory"

This error happens when there is no grub2 directory and is caused by
line 20 in payloads/external/GRUB2/Makefile where a shell command is
used to check the state of the git repo for grub2. Thought the target
for this code (checkout) is not executed by 'make clean' the shell
evaluates the command as part of the Makefile sourcing and encounters a
missing directory.

This patch fixes this error by checking for the project directory before
the git status of the repo is evaluated.

Change-Id: Ieaa919e1ee5ec2a1ec3c840fa07a6ec16d230e88
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-12 18:22:19 +00:00
Werner Zeh 1b8102474e mb/siemens/mc_apl6: Enable VT-d feature
This mainboard needs VT-d to be enabled. Do so in devicetree.

Change-Id: I9f2f733163be019ac329660d7633b48c5d7896f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-11-12 18:21:57 +00:00
Patrick Georgi 71a94301c0 Documentation: Add more entries to 4.11 release notes
Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12 18:21:45 +00:00
Elyes HAOUAS 8a0dccc02b vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded
This cleans .config from unused UDK_VERSION's symbol.

Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34536
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12 12:20:16 +00:00
Subrata Banik 6de0c141fd soc/intel/tigerlake: Remove deprecated CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
CB:36620 moves common cbmem_top_chipset to fsp driver hence no need to have
dedicated kconfig as in SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM

Change-Id: I3914993754ba409867399e903e5d13e929a92e1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-12 09:29:42 +00:00
Hung-Te Lin de6f121897 mb/google/kukui: Add new configs 'damu' and 'kappa'
New boards introduced to Kukui family.

BUG=None
TEST=make # select damu and kappa

Change-Id: I7154aeee921114b7d12bf586adca250df19a3883
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-11-12 08:27:59 +00:00
Bill XIE 72f13e534b ec/lenovo/h8: Make dock init in ramstage fully mainboard-specific
Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.

Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.

Tested on X200. Testing on other affected targets may be necessary.

Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-12 08:26:42 +00:00
Patrick Rudolph 9764bc126e mb/*: Fix default fmap with VBOOT_SLOTS_RW_A enabled
Don't select the VBOOT fmap as default if VBOOT is disabled.

Fixes a regression introduced by f8251b98
"mb/emulation/qemu: Add VBOOT support" where the default Kconfig settings
wouldn't allow the qemu boards to run.

Also fix the Supermicro x11-lga1151 series boards.

Change-Id: I90414e2cc7e4c4a6ad67014bd4a7f9c8ff4da389
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36707
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12 08:25:45 +00:00