Commit Graph

14 Commits

Author SHA1 Message Date
Jonathan Neuschäfer 7719d50352 Documentation/Intel: Adjust heading levels
Adjust the headings so that there is only one h1 tag per file.

Change-Id: I53f9ee47957fcde521b64c0123dac10f051c681c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-17 17:18:07 +00:00
Martin Roth 4b18a922f0 Documentation: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Unfortunately, some external websites and projects are spelling coreboot
with an uppercase C, so references to those pages can't be changed
without breaking the link.

Change-Id: I79824da8a9ed36a1e4fe23a1711a89535267bf5f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-06-12 04:06:40 +02:00
Paul Menzel a8843dee58 Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.

Run the command below to replace all occurences.

```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```

Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07 12:04:50 +02:00
Lee Leahy e9a6d1a813 Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:06 +01:00
Lee Leahy 4ee073d476 Documentation/Intel: More CorebootPayloadPkg documentation
Add more documentation on the features that the EDK-II
CorebootPayloadPkg is using.  Add 8254 and 8259 documentation
links.  Add EDK-II documentation links.

TEST=Boot CorebootPayloadPkg to shell prompt

Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:59:26 +01:00
Lee Leahy ca20b5fa6f Documentation/Intel: Add ACPI link and more FADT documentation
Add a link to the ACPI specification.
Update the FADT table to better describe the use and ACPI specification
reference for the various fields.

TEST=None

Change-Id: I77cd925800d71398be6d677de48874099ea26479
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13765
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-29 04:56:23 +01:00
Lee Leahy bf08da27d5 Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24 15:55:42 +01:00
Lee Leahy de8c7e39bc Documentation: x86 device tree processing and memory map
Add documentation on:
*  FSP Silicon Init
*  How to start the x86 device tree processing for ramstage
*  Disabling the PCI devices
*  Generic PCI device drivers
*  Memory map support

TEST=None

Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:02 +01:00
Lee Leahy fcf776fd02 Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup.

TEST=None

Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:25 +01:00
Lee Leahy 66decf1644 Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:03 +01:00
Lee Leahy 7e0078b990 Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image.

TEST=None

Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13442
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:53:11 +01:00
Lee Leahy e8424cf10f Documentation: Fix links to Intel/documentation.html
Fix links to the documenation.html page which was renamed from
x86Documenation.html.

TEST=Verified documentation links and searched for x86Documenation.html

Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:46 +01:00
Lee Leahy 380e167680 Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support.

TEST=None

Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13441
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-04 19:30:40 +01:00
Lee Leahy c1e4f89953 Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.

TEST=None

Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 15:54:43 +01:00