Commit Graph

52871 Commits

Author SHA1 Message Date
Matt DeVillier e1ff8756cf drivers/sof: Add support for max98357a with 4-ch output
Will allow boards using this speaker configuration to correctly specify
their output type.

TEST=tested with rest of patch train

Change-Id: Iefcfc928e2611f533af1a2962ec2761ec1b7bf3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15 16:35:34 +00:00
Jeremy Compostella 33f9170dae commonlib: compiler.h: Add __printf macro
This patch adds the `__printf' macro to comply with checkpatch
following warning:

    Prefer __printf(1, 2) over __attribute__((format(printf, 1, 2)))

BRANCH=firmware-brya-14505.B
TEST=Successful compilation with `__printf(1, 2)' instead of
     `__attribute__((format(printf, 1, 2)))'

Change-Id: Ic2d90478ab0955c2ad0955e8cff5be76bfb2e741
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75159
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15 16:35:27 +00:00
Sean Rhodes 9d7e25e544 3rdparty/blobs: Advance submodule pointer
This contains the following commits:

* 9df5910: mb/starlabs/starbook/adl: Update EC binary to 1.13
* 65c8e9a: soc/mediatek/mt8188: Add scramble switch and fix 1RK register
           bit
* 1a4c51c: soc/mediatek/mt8188: Add scramble switch for dpm version 0.2
* 076cdd1: soc/mediatek/mt8188: Update MCUPM firmware from v1.01.03 to
           v1.01.04
* 2be5f15: soc/mediatek/mt8186: Update SSPM firmware from v2.0.0 to
           v2.0.1
* 01ba156: mb/google/skyrim: Add RO SPL table
* ce5566f: soc/mediatek/mt8186: Update SSPM firmware from v1.0.0 to
           v2.0.0

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iee7b479f305b77f4e6ab5e53a0b74cebdc653599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-15 13:29:37 +00:00
Karthikeyan Ramasubramanian f5a2ce5c6a mb/google/myst: Re-organize the FMAP layout
By moving certain FW UI assets from RO to RW sections, 4 MiB is
sufficient for RO section. Split the resultant available 4 MiB equally
between 2 RW sections. This will help in getting to 16 MiB SPI flash for
the mainboard.

BUG=b:281567816
TEST=Build Myst BIOS image with the updated layout.

Cq-Depend: chromium:4519688
Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-15 13:29:04 +00:00
Michał Żygowski eb9f1e1438 mb/msi/ms7d25: Update USB port macros
Update USB port macros:
- change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1,
  HUB to USB 2.0 headers, HUB to rear USB 2.0
- change USB type C header to LONG which caused hard lockups on the
  port making it unable to enumerate in UEFI Payload and Linux
- add empty definitions for USBr ports

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15 13:22:39 +00:00
Sheng-Liang Pan 465fbbe93e mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbi
copy from dibbi since taranza base on dibbi,this is only for first
initial configuration, will update the more setting afterward.

BUG=b:277664211
BRANCH=dedede
TEST=build

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-05-15 00:16:06 +00:00
Sheng-Liang Pan cbbdaf4524 mb/google/dedede/var/taranza: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.

BUG=b:277664211
BRANCH=dedede
TEST=build

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-15 00:15:59 +00:00
Felix Singer a5353a9408 docs/releases/4.20: Update release notes
Change-Id: If5627cef5293c160e91ff85297abe695064f1bd1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74981
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-15 00:03:27 +00:00
Felix Singer f61b12d853 docs/releases: Add 4.21 release notes template
Change-Id: Ibb4eaba6be088e20c76a8329847148c1d4ff8c04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75187
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14 23:21:02 +00:00
Felix Singer 4afa8defc9 docs/vboot: Update list of boards supported by vboot
Change-Id: Ib797c17183ca48131713288c618c4c20496583fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75215
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2023-05-14 23:05:57 +00:00
Felix Held b2f2b53fb2 acpi/acpigen: add comment about byte 0 in acpigen_resource_*word
Since it's not obvious, add comments to acpigen_resource_word,
acpigen_resource_dword and acpigen_resource_qword to clarify out what
the magic number in byte 0 means. The most significant bit of byte 0
indicates if it is a small or large resource data type. In the case of
the MSB being 0, it's a small resource data type (aka type 0), and the
other bits encode bit the type and size of the item; if the MSB is 1,
it's a large resource data type (aka type 1), and the other bits just
encode the type and there are two separate bytes to encode the size.
Beware that the large resource's data type values in the ACPI
specification don't include the MSB that's set, but only the 7 lower
bits.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6a6c9fb1bcde232122bb5899b9a0983ef48e12b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14 17:51:11 +00:00
Arthur Heymans d1c61a8e70 arch/x86/ioapic.c: Increase the number of bits for ioapic ID
In practice hardware can use larger numbers.

Change-Id: I6e9ddd1ebd396c37e25eb3019f981d45d9c5e062
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-14 13:00:25 +00:00
Anil Kumar 0e1f08d1fb mb/google/rex: Add variant specific SOC chip config update function
This patch adds support for variant specific chip config update similar
to commit 061a93f93d ("mb/google/brya: Add variant specific soc chip config update").

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14 12:54:43 +00:00
Kun Liu 6f6353d570 mb/google/rex/var/screebo: Add initial devicetree config
add initial devicetree config for screebo

BUG=b:276814951
TEST=emerge-rex coreboot

Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14 12:54:07 +00:00
Ruihai Zhou d5c1e13304 mb/google/corsola: Add support for MIPI panel
The detachable Starmie will use MIPI panels, which require reading
serializable data from the CBFS. So we add MIPI panel support to the
display configuration and align the configuration sequence with the
panels that use MIPI bridges.

The PMIC Datasheet:
TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf

BUG=b:275470328
BRANCH=corsola
TEST=emerge-corsola coreboot chromeos-bootimage and display normally

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-14 12:52:21 +00:00
Frans Hendriks 946d17a2a5 mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_list
Error message ´Cannot map compressed file config without cbfs_cache' is reported.

Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list.
Will be added to verified items by CB:74752.

BUG=NA
TEST=booting and verify log on facebook FBG1701

Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14 12:51:49 +00:00
Dtrain Hsu b233bd70c2 mb/google/nissa/var/uldren: Add wifi sar table
Add wifi sar table for uldren

BUG=b:279679700
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-14 12:51:25 +00:00
Simon Zhou f5fe5878ad screebo: fix the lp5ccc config from 0x55 to 0xaa
BUG=b:278022971
TEST=verified on screebo

Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14 12:51:03 +00:00
Fred Reitberger 5c1c7b6904 soc/amd/phoenix/Kconfig: Update default soft fuse bits
Set the default soft fuse bits to the recommended values

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2354aefe90a08eaef95a68926806d11a9118c3de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-14 12:49:34 +00:00
Fred Reitberger 096e04c935 mb/google/myst/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte
addressing mode, so ensure the driver exits that mode for regular
operation.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-14 12:49:22 +00:00
Kyösti Mälkki ece06dc2d1 sb/intel/bd82x6x,ibexpeak: Move UPRWC definition
Locate it with all the other PM IO registers.

Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14 12:42:55 +00:00
Kyösti Mälkki ab368d96d7 sb/intel/lynxpoint: Remove GPE0_{EN,STS}_2 defines
By ACPI specification, those follow GPE0_EN bits in the register space.
Use sizeof() to replace the 2/4 offset previously used.

Change-Id: I27ada0b19b2cf5e8eca71f48bf103dcab1b3cc11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14 12:42:45 +00:00
Arthur Heymans 23d4614d8a Makefile.inc: Warn about set but unused variables with GCC
Clang was already warning about this. Synchronize the behaviour between
both compilers.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3331a7437b17ab5ac97cef94511bb29c020bdff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75032
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-14 07:22:50 +00:00
Eric Lai 909829e304 mb/google/hades: update TPM IRQ in early gpio table
TPM IRQ should be A20 not A13. RAM table is correct.

BUG=b:282164589
TEST=able to boot up

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14 03:26:06 +00:00
Eric Lai 3707400f80 mb/google/hades: Correct TPM I2C bus to 3
Follow schematic to correct I2C bus.

BUG=b:282164589
TEST=able to boot up

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-14 03:25:55 +00:00
Benjamin Doron 21af6b4431 payloads/external/edk2: Verbose builds with coreboot build-system
Rather than requiring another Kconfig symbol to be set, reuse the same
`make V=1` command argument. This simplifies rebuilds with a single
point of reference.

Also, this means that coreboot doesn't have to be rebuilt due to Kconfig
changes.

Change-Id: I9eba86b234768641a215095b8657e9d07832b1b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-13 20:07:20 +00:00
Matt DeVillier b8a0e64d78 drivers/net/r8168: add ACPI _STA field entry
Add _STA field entry for r8168 ACPI device and set to
ACPI_STATUS_DEVICE_HIDDEN_ON in order to hide device from
OS (Windows) as there is no driver needed (or available).
Windows correctly attaches drivers to the PCIe device, the
separate ACPI device is unused and unneeded.

Linux is unaffected as it does not use the ACPI device status.

Change-Id: Ib7ae99fffcb00e71421b93c2794119841aa239d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75177
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 20:06:58 +00:00
ReddestDream 56a3442dd8 mb/samsung/lumpy: Adjust touchpad ACPI for Windows drivers
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.

TEST=build/boot samsung/lumpy, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.

Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13 18:38:09 +00:00
ReddestDream 525154d16e mb/google/parrot: Adjust touchpad ACPI for Windows drivers
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach.

TEST=build/boot google/parrot, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.

Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 18:37:54 +00:00
Matt DeVillier a4eba7f09f mb/google/butterfly: Adjust touchpad ACPI for Windows drivers
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.

TEST=build/boot google/butterfly, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.

Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13 18:37:32 +00:00
Matt DeVillier 8203752e89 mb/google/stout: Use board-specific PS2M HID/CID to enable multitouch
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO
default, so that Windows installs a multitouch-capable driver rather
than the standard PS2 mouse driver.

TEST=build/boot Win11 on google/stout, verify trackpad is multitouch
capable.

Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 18:36:33 +00:00
Matt DeVillier 2323282778 sio/smsc/mec1308: fix SIO/PS2 keyboard ACPI for Windows
Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.

TEST=build/boot Win11 on samsung/lumpy, verify keyboard functional.

Change-Id: I7b6b09da1a3fdc34ef43789c699f7fd22b4b655b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13 18:36:03 +00:00
Matt DeVillier 625066e4f4 ec/quanta/ene_kb3940q/acpi: Fix PS2K under Windows
Add _HID to parent SIO device so Windows can find the PS2K, and
remove _ADR since HID and ADR are mutually exclusive.

TEST=build/boot Win11 on google/butterfly, verify keyboard functional.

Change-Id: I772ceef1b439cfd4e2740e53362bee9d494fb36d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13 18:35:44 +00:00
Felix Held f0a8b042c9 acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRING
In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13 18:34:44 +00:00
Felix Held 3d19aa9ce8 soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide MISC device
Don't set bit 2 of the return value of the _STA method in order for
Windows not to show a warning about an unknown device in the device
manager for this device.

TEST=The unknown device with device instance path ACPI\AMD0040\3
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If005f06843956004c281fd70cf364171148cb9ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 18:33:40 +00:00
Felix Held 39a98260ff soc/amd/*/acpi/mmio.asl,sb_fch.asl: change AAHB's _STA back to method
Commit 396fb3db74 ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB
device") didn't only change the visibility of the device, but also
changed the _STA method to a name. While this worked, the specification
says that _STA is supposed to be a method, so change it back to being a
method.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 18:33:20 +00:00
Arthur Heymans bba14fe497 soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register
Clang complains about this.

Change-Id: I2d761d2fa946f171033220ab7b2e399cf359782a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-13 17:22:16 +00:00
Arthur Heymans 1443137d5c vendorcode/mediatek/mt8195: Fix set but unused variables
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:19:53 +00:00
Arthur Heymans 9781411719 vendorcode/mediatek/mt8195: More sure ucDoneFlg is initialized
One some codepaths ucDoneFlg is not initialized. This fixes a clang
warning.

Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:19:27 +00:00
Arthur Heymans a66b469107 vendorcode/mediatek/mt8195: Make order of operators more explicit
Clang warns about this.

Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:19:15 +00:00
Arthur Heymans 8d7eff32af vendorcode/mediatek/mt8195: Fix superfluous brackets
Clang warns about this.

Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:19:05 +00:00
Arthur Heymans 3c2fa3519c vendorcode/mediatek/mt8195: Fix casting enum of different types
Clang warns about this.

Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:18:51 +00:00
Arthur Heymans e9d9c1e898 vendorcode/mediatek/mt8195: Fix set but unused variables
The clang compiler warns about this.

Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 17:18:40 +00:00
Arthur Heymans 94efac50ef soc/cavium: Guard gcc specific compiler flag
TEST: BUILD_TIMELESS=1 remains the same.

Change-Id: I740b59574303145fc673a97556367daefe8d1540
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74540
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 09:31:39 +00:00
Arthur Heymans cef0e0ad6f vendorcode/cavium: Fix additions to string
The clang compiler is confused about adding integers to strings. Adding
brackets around the macros fixes this.

TEST: BUILD_TIMELESS=1 remains the same.

Change-Id: I2ea17322352d977bf0ec3ee71b14463fa218d07c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74541
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13 09:31:00 +00:00
Arthur Heymans 4ffce7e8ac soc/mediatek/mt8195/apusys_devapc.c: Fix unsigned comparison
Clang warns about unsigned comparison below 0. Use the enum value itself
to fix this warning.

Change-Id: I12fccff2fb7d43fd4582afd518a7eab632908a5f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74553
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 09:30:21 +00:00
Arthur Heymans bd429063d9 vendorcode/mediatek/mt8192: Fix set but unused variables
TEST: BUILD_TIMELESS=1 binary remains the same.

Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 09:29:28 +00:00
Arthur Heymans a9737abf78 vendorcode/mediatek/mt8192: Fix set but unused variables
The binary does change on these with BUILD_TIMELESS.

Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-13 09:20:34 +00:00
Angel Pons 7d6362d56b mb/prodrive/hermes: Ensure VMX setting is applied
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can
be locked. The MSR remains locked after a non-power cycle reset, though.
If the MSR is locked, coreboot bails out and leaves VMX in the state it
was found. Because of this, changes to the VMX enable option in the BMC
only take effect after the system is power cycled.

This behaviour is highly undesirable because users are likely not aware
that a power cycle is required for changes to VMX state to take effect.
So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the
current VMX state does not match the requested state, then issue a full
reset. This will power cycle the system and unlock the MSR, so that the
desired VMX state can be programmed into the MSR. This is checked early
to avoid needlessly doing time-consuming operations (running FSP) twice
if we know we will need to power cycle the system anyway.

Note that a user may change the VMX setting after the newly-added check
but before the setting is read in ramstage to program the MSR, but this
is a non-issue as firmware settings need a reset to take effect anyway.

TEST: Toggle VMX setting in BMC and reboot without power cycle, observe
      coreboot automatically issues a power cycle reset because the MSR
      is locked and the VMX state differs. Verify that the system boots
      properly with VMX in the correct state after having power cycled.

Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-13 09:19:32 +00:00
Felix Held c391bff443 cpu,nb/amd/pi/00730F01: dynamically generate CPU devices
Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.

TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13 00:14:32 +00:00