Commit Graph

182 Commits

Author SHA1 Message Date
Duncan Laurie d338b46504 chromeec: Add event methods for EC requested throttle
Two new events possible from the EC for starting and stopping throttle.

These are handled in a per-board method that is defined under the
thermal zone.  This is not quite where I wanted it but the scoping
rules in ACPI don't let me have a defined external object in the
same scope.

Change-Id: I766f07b4365b29df3daa8e45e88f7c38c645c287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63988
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4415
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 12:02:14 +01:00
Vladimir Serbinenko f422a443d7 ec/lenovo/h8: Enable 3G modem
Just like bluetooth and wlan it need to be enabled in EC.
Set the appropriate bit in EC if CMOS config says so.

Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4516
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-19 08:58:16 +01:00
Vladimir Serbinenko 2c87668914 ec/lenovo/h8: Fix peripheral init without CMOS config
Currently H8 skips important init if unable to access CMOS config.
Change default to enable all features to have a sane system without
using CMOS config.

Change-Id: I4448ccd21beae8ad23eb22391770c6fe3b83e3b4
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4515
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-15 17:49:23 +01:00
Shawn Nematbakhsh d0a6a38bb7 chromeec: Allow get_board_version to be called from romstage.
We will soon need to call google_chromeec_get_board_version to determine
correct DDR SPD. We must do so before DDR is initialized, so allow this
function to be called from romstage.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: I882d84e38d11bf66067193a6f408f941f2cf8a81
Reviewed-on: https://gerrit.chromium.org/gerrit/61191
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:04:00 +01:00
Vladimir Serbinenko 161e9cc56b Introduce a config whether dock is inited in romstage or not
Instead of depending on exact mobo configure general characteristic whether
dock is configured in romstage or ramstage.

X60 and T60 have superio in dock so it needs to be inited to get serial, so
it should be inited in romstage.

On X201 there is nothing useful that early in boot but it's needed to init more
to get dock working, in particular EC init needs to be done first.
Change-Id: If5072e3dec883a94cd2d5643a92f7f6c3c9feee9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4294
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 22:16:18 +01:00
Vladimir Serbinenko dfc0881272 EC H8: remove dependence on IS_X201
Instead define brightness up/down function and gfx device and use
preprocessor magic to glue it together.

Change-Id: I03074ae07b33c1546d229efc3e80606ddbee6300
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-12-02 22:15:45 +01:00
Alexandru Gagniuc 72dccce0c9 global: Fix usage of get_option() to make use of CB_CMOS_ codes
Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.

Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 22:11:20 +01:00
Peter Stuge 77a5abe780 ec/lenovo/h8: Add h8_build_id_and_function_spec_version()
The function reads the Build ID and the supported function specification
version from the running EC firmware, and stores a text representation
in the provided output buffer.

Change-Id: I3b647d7f315c9b4922fa9a9c5167a80f6d82e753
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3617
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 20:04:39 +01:00
Vladimir Serbinenko eb13b6f3e8 H8: Move EC GPE declaration to mainboard
Change-Id: Iefc481f09268dd15bbc3cbfa8bdd110d44383f6a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4281
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-01 13:36:25 +01:00
Vladimir Serbinenko 969553e574 Add declaration of dock registers 1, 2 and 3.
Needed to make dock work on X201.

Change-Id: Id0b32266cacf04bb48530bedf50818c268f947ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4081
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-25 07:00:11 +01:00
Vladimir Serbinenko d26558cf5b Lenovo hotkeys support
Implement proprietary lenovo ACPI hotkeys

Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4055
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 00:20:04 +01:00
Vladimir Serbinenko 219f068ae3 Change EC GPE on X201
X201 has GPE at 0x11 (17) instead of 28.

Tested on X201.

Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4053
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23 23:41:12 +01:00
Vladimir Serbinenko e2b6795e04 Call X201 dock hooks in EC code
Unlike on X60/T60 dock has to be inited at the same time as EC.

Change-Id: If6eb3140c871859ce99027a50908f72bcc560243
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4082
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-23 13:09:56 +01:00
Nico Huber ca4f073f8e ec/kontron/it8516e: Add sanity checks for values from nvram
Change-Id: Ie52d80fc8657064efdcec51c31dc9309fcc28121
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3787
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:22:12 +02:00
Nico Huber 1f9f67864a ec/kontron/it8516e: Comment low-level EC functions
Change-Id: I5f75998356554e08f8c9920e7612494e4710ab15
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3786
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:21:55 +02:00
Nico Huber 260c33ba56 ec/kontron/it8516e: Remove some unsafe bit shifting
The EC expects the temperature in 64ths degree C. Alter
it8516e_set_fan_temperature() to just export this interface and
make the calculation more obvious.

Change-Id: Ibe241b7909f4c02b30b1e1200a1850d47695a765
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3785
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-29 23:21:11 +02:00
Nico Huber 9ce71b3cca ec/kontron/it8516e: Add PWM limits option
Add an option to set minimal and maximal PWM percentages when the fan is
in temperature controlled mode. Also fix a non-ascii flaw.

Change-Id: I85ae244bee2145bf17d6c29e93dd4871540985c8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3774
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:19:41 +02:00
Nico Huber 942b6c2117 ec/kontron/it8516e: Correct fan setting for PWM mode
The EC firmware expects a 255th while we provide a percentage.

Change-Id: Ib06a061b431ac728329043179800729e39e6166b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3773
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:18:45 +02:00
Nico Huber 6d6a2ac055 ec/kontron/it8516e: Add option for external temperature sensor
The IT8516E firmware of Kontron supports some selected external sensors
attached to the EC via SMBUS or GPIO16.

Change-Id: I4c451c360a393e916430e3bea04a95847455cef7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3772
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:17:58 +02:00
Gabe Black 9f96aa6b5e chromeec: Add a function to send passthrough i2c messages.
Change-Id: I576d0dbf65693f40d7d1c20d3d5e7a75b8e14dc9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/3752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:18:30 +02:00
Hung-Te Lin 0ee7062e30 ec/google: Support ChromeOS EC on SPI bus.
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface
(see spi-generic.h) to exchange data.

Note: Only EC protocol v3 is supported for SPI bus.

Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:15:57 +02:00
Hung-Te Lin e946f981a4 ec/google: Support Chrome EC protocol version 3.
Add the new Chrome EC protocol version 3 to Coreboot.

Note, protocol version 3 is not applied on any bus implementations yet.
LPC (x86) and I2C (arm/snow) are still using v2 protocol.  The first one to use
v3 protocol will be SPI bus (arm/pit).  LPC / I2C will be updated to v3 only
when they are ready to change.

Change-Id: I3006435295fb509c6351afbb97de0fcedcb1d8c4
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3750
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:15:50 +02:00
Hung-Te Lin 23fb9979d9 ec/google: Generalize communication protocol support in EC drivers.
Since EC protocol v3, the packet format will be the same for all buses (inclding
I2C, SPI, and LPC). That will simplify the implementation in each individual bus
driver source file.

To prepare for that, we will move the protocol part into crosec_proto.c:
crosec_command_proto, with bus driver in callback "crosec_io".

Change-Id: I9ccd19a57a182899dd1ef1cd90598679c1546295
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3749
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:15:42 +02:00
Hung-Te Lin ce7a5a790b ec/chromeec: Merge upstream V3 structure and constant definition.
Chrome EC protocol V3 has several new command structure and constants defined.
Simply cherry-picking changes from upstream.

Change-Id: I7cb61d3b632ff32743e4fa312e0cc691c1c4c663
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3748
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:48:20 +02:00
Bill Richardson e221aad27f ec: Reserve correct ioport regions for Chrome OS EC to use
The LPC-based ChromeOS EC uses several ioport regions to communicate with
the AP. In order for the new unified userspace access method to work, we
need them to be reserved by the BIOS.

Before /proc/ioports shows:

  0800-0803
  0804-08ff

We'd like just a single 256-byte region at 0x800, but ASL can't handle that.
So this will work:

  0800-087f
  0880-08ff

Change-Id: I3f8060bff32d3a49f1488b26830ae26b83dab79d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: http://review.coreboot.org/3746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:45:11 +02:00
Duncan Laurie 6d16c437fc slippy/falco/peppy: Enable SERIRQ continuous mode
The Chrome EC still does not tolerate SERIRQ in quiet mode
and so the keyboard does not work properly.

Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/3745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:44:31 +02:00
Duncan Laurie 7cced0d20e ec: Add romstage function for checking and rebooting EC
Now that we are executing VbInit() in coreboot we can end up
in a situation where the recovery reason is consumed during
VbInit (end of romstage) and then the EC is rebooted to RO
during ramstage EC init, thereby losing the recovery reason.

Two possiblities are to remove the EC check+reboot from ramstage
and let it happen in depthcharge.  This however means that the
system has to boot all the way into depthcharge and then reboot
the EC and the system again.

Instead if we do a check in romstage before VbInit() is called
then we can reboot the EC into RO early and avoid booting all
the way to depthcharge first.

This change adds a ramstage version the EC init function and
calls it from the shared romstage code immediately after the
PCH decode windows are setup.

Change-Id: I30d2a0c7131b8e4ec30c63eea36944ec111a8fba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/3744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:44:22 +02:00
Duncan Laurie 433432b654 chrome ec: Update EC header from EC repository
- Updated ec_commands.h is copied in directly from EC repo
- Removed "old" interface and update resources for "new" interface
- Updated temp sensor constants and added "not calibrated"
- Update mainboards to remove check for EC_SWITCH_KEYBOARD_RECOVERY

Change-Id: Ic93c1914f86b6f5bc224178270624ed92b5c1e15
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/3743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:44:09 +02:00
Duncan Laurie 045222f312 ec: Remove hardcoded GPI offset in EC SCI
With LynxPoint-LP the SCI GPE is no longer a GPIO
that is offset by 16.  Remove the Add and fix up
the link definition so it is still accurate.

Change-Id: I091141183a09345b5ffe28365583e48019f9f5e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/3742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 21:42:51 +02:00
Martin Roth 8940d3e2a7 ec: Fix spelling
Change-Id: I5e4d35572c43f07bec5ec0bcd75c717723228e2f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3757
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:18:06 +02:00
Gabe Black 3fb30eeb14 ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.
The default for this variable should be n, it should only depend on
EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when
needed. This prevents it from being turned on when the EC bus is SPI.

Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3737
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:38:55 +02:00
Peter Stuge d0b04003d0 Revert "Radio and dock support in EC on X60 and X201"
This reverts commit 7d1ebbff5a

Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3616
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-08 06:18:50 +02:00
Nico Huber 9cb0941cb2 pnp: Unify some alignment to ease autogenerating patches
Most PnP drivers align the initialization of their `device_operations`
with spaces. Unify this, so next autogenerated patches always match the
alignment.

Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3479
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 18:11:35 +02:00
Vladimir Serbinenko 26419285bf Avoid tripping overheat alarm on X201 before ME boots
Until ME boots (which takes seconds on X201) the reported temperature
is 128 °C which triggers Linux overheat alarm which shuts down.
Pretend temperature is 40°C until ME boots.

Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3404
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:51 +02:00
Vladimir Serbinenko fe50d0bcfe Make acpi/ec.c usable in romstage
On X201 to enable EHCI debug you need to go through EC if USB power is
disabled so we need to inclue ec.c.

Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3405
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:07 +02:00
Vladimir Serbinenko 7d1ebbff5a Radio and dock support in EC on X60 and X201
Enable UMTS on Lenovo X60 and X201.
Enable radios if no options are available.
Enable dock on Lenovo X201.

Based on my X201 branch.

Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:28:25 +02:00
Nico Huber 7bb02512d9 ec/acpi: Add ACPI methods for generic EC access
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language
(ASL). These functions are used to control embedded controllers with the
standard ACPI interface (mostly through i/o ports 0x62 / 0x66).

The following methods are implemented and tested against the power
managements channels of a ITE IT8516E embedded controller:
 * WAIT_EC_SC           Wait for a bit in the EC_SC register
 * SEND_EC_COMMAND      Send one command byte to the EC_SC register
 * SEND_EC_DATA         Send one data byte to the EC_DATA register
 * RECV_EC_DATA         Read one byte of data from the EC_DATA register
 * EC_READ              Read one byte from ec memory (through cmd 0x80)
 * EC_WRITE             Write one byte to ec memory (through cmd 0x81)

To use the provided methods, one should include `ec/acpi/ec.asl` in the
EC device code. Prior doing so, two macros should be defined to identify
the used i/o ports:
 * EC_SC_IO     I/o address of the EC_SC register
 * EC_DATA_IO   I/o address of the EC_DATA register

Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3285
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-06-06 21:19:28 +02:00
Nico Huber a53266bee0 ec/kontron/it8516e: Add it8516e EC driver
This driver communicates with the IT8516e on the Kontron KTQM77.
Since we don't know if the firmware and protocol are standard for
the chip or customized to the board, call it kontron/it8516e.

Change-Id: I7382172c6d865d60106c929124444821a07a5184
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:39:52 +02:00
Stefan Reinauer ab348528b5 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT
This used to contain the path for the EC include files, but
those files are included in coreboot now.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369
Reviewed-on: https://gerrit.chromium.org/gerrit/47606
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3057
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 02:47:23 +02:00
Hung-Te Lin 76720d064d ec/google: Move plug-n-play initialization to LPC protocol.
"Plug-n-play" is not supported on all platforms using Google's Chrome EC.
For example, EC on I2C bus will need explicit configuration and initialization.
So move the plug-n-play initialization to the LPC implementation.

Verified by building Google/Link (with EC/LPC) successfully.

Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3089
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-16 01:07:16 +02:00
Hung-Te Lin 6bfbb33a64 ec/google: Support Google's Chrome EC on I2C interface.
Google's Chrome EC can be installed on LPC or I2C bus, using different command
protocol.  This commit adds I2C support for devices like Google/Snow.

Note: I2C interface cannot be automatically probed so the bus and chip number
must be explicitly set.

Verified by booting Google/Snow, with following console output:
  Google Chrome EC: Hello got back 11223344 status (0)
  Google Chrome EC: version:
     ro: snow_v1.3.108-30f8374
     rw: snow_v1.3.128-e35f60e
    running image: 1

Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3074
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16 00:32:49 +02:00
Hung-Te Lin a904f9ef69 ec/google: Isolate EC bus protocol implementation.
The Chrome EC can be connected by different types of bus like LPC / I2C / SPI,
and the current implementation is only for LPC.

To support other types, we must first isolate the LPC protocol stuff and add
configuration variable (EC_GOOGLE_CHROMEEC_LPC) to specify bus type.

Verified by building google/link (with chromeec) configuration successfully.

Change-Id: Ib2920d8d935bcc77a5394e818f69e9265e26e8a0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3068
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-12 04:57:39 +02:00
Stefan Reinauer 24d1d4b472 x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:00:09 +01:00
Stefan Reinauer 7e56855963 Support ITE IT8518 embedded controller running Quanta's firmware
Change-Id: Ib406b9d5005243d79eea5d2c0c6c86b5aa949891
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2721
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-14 04:54:21 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Stefan Reinauer d6682e88af Add support for Google ChromeEC
Google ChromeEC is an EC with completely open source firmware.
See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary
for the EC firmware source code (aka more information about the ChromeEC)

This patch adds support for the ChromeEC on coreboot's side.

Great thanks to the ChromeEC team for this amazing work. It's another
important milestone towards a free and open firmware stack on modern
hardware.

Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec
Signed-off-by: Stefan Reinauer <reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/2481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-22 23:10:01 +01:00
Stefan Reinauer d7bd4eb003 Add support for "Butterfly" Chromebook
We're happy to announce coreboot support for the "Butterfly"
Chromebook, a.k.a HP Pavilion Chromebook.

More information at:
http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html

This commit also includes support for the ENE KB3940Q embedded controller
running on Quanta's firmware.

Change-Id: I194f847a94005218ec04eeba091c3257ac459510
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2359
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2013-02-11 22:02:32 +01:00
Stefan Reinauer d8a5fd2321 Add support for ENE932 EC w/ Compal firmware
Change-Id: I19b03139e7edfee6ff3e0bcef735bb36bfadc354
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2024
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12 06:02:04 +01:00
Patrick Georgi 23f38cd05c Get rid of drivers class
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.

These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.

With ramstage.a gone, we can drop this special class, too.

Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:00:49 +01:00
Kyösti Mälkki fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
Stefan Reinauer 57879c9bd1 Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
   compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
   the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
   romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage

We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.

So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
 #ifndef __PRE_RAM__
        .ops = 0,
 #endif
        .bus = &_dev7_links[0],
        .path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
        .enabled = 0,
        .on_mainboard = 1,
        .subsystem_vendor = 0x1ae0,
        .subsystem_device = 0xc000,
        .link_list = NULL,
        .sibling = &_dev22,
 #ifndef __PRE_RAM__
        .chip_ops = &southbridge_intel_bd82x6x_ops,
 #endif
        .chip_info = &southbridge_intel_bd82x6x_info_10,
        .next=&_dev22
};

Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 18:05:39 +02:00
Stefan Reinauer 020b22a5c4 Add EC component for SMSC MEC1308/1310
Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/828
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-02 18:42:40 +02:00
Sven Schnelle bba0346ef5 X60/T60: Add option to enable/disable bluetooth
Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/598
Tested-by: build bot (Jenkins)
2012-01-31 18:03:40 +01:00
Sven Schnelle d5992b8dd1 Lenovo X60/T60: add first_battery setting
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.

Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 09:41:46 +01:00
Sven Schnelle d0ea6789e6 Lenovo H8: Fix h8_set_audio_mute()
Logic is inverted (if argument is true, one would expect that
mute is enabled) and the wrong bit was used (1 instead 0)

Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/334
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25 17:48:41 +02:00
Sven Schnelle b538110532 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.

To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.

Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)
2011-10-20 16:06:35 +02:00
Sven Schnelle 6901b561eb Lenovo H8: Always clear audio mute
The mute bit is set by ACPI before poweroff/going to suspend.
So clear it after resume, to have working volume control
even if the ACPI doesn't clear it on resume.

OSPM should control Audio mute with ec bit 0x30:6, so it is
safe to clear this bit even if the user has audio muted.

Change-Id: I18bebe532bf21cfb61b3d294a396bf15012f9f1a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/162
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2011-08-19 14:17:06 +02:00
Sven Schnelle d8b60a0f2d T60: undock on external power loss
If power is unplugged/lost, we should undock the docking station.
The power loss can also be caused by the fact that the user removed
the thinkpad from the docking station without pressing the Undock button/hotkey
first. Without undocking it on this event, the thinkpad LPC switch will still
connect the Docking connector, which causes crashes when docking it again.

Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/62
Tested-by: build bot (Jenkins)
2011-06-23 14:12:26 +02:00
Sven Schnelle 3aefab54e1 H8: add missing License Header
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/56
Tested-by: build bot (Jenkins)
2011-06-22 17:11:38 +02:00
Sven Schnelle d74f97e310 PMH7: add missing License Header
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/55
Tested-by: build bot (Jenkins)
2011-06-22 17:02:03 +02:00
Sven Schnelle 86e1aea3e6 Lenovo H8 EC: add usb_power_enable()
Can be used to disable/enable Power output on USB ports.

Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/37
Tested-by: build bot (Jenkins)
2011-06-16 17:00:12 +02:00
Sven Schnelle 5d9a83c9f0 log ec data with DEBUG_SPEW
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)
2011-06-12 17:13:51 +02:00
Sven Schnelle 1b8068e244 H8 EC: add volume CMOS setting
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
2011-06-09 10:05:46 +02:00
Sven Schnelle 51e1bc3a7b T60/PMH7: move 'touchpad' option to pmh7
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.

Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-07 22:43:14 +02:00
Sven Schnelle 95ebe66f7f Thinkpad: Enable Battery events
Enable the following events for battery objects on
Thinkpad X60/T60:

24: BAT0 critical
25: BAT1 critical
4A: BAT0 present
4B: BAT0 state change
4C: BAT1 present
4D: BAT1 state change

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-28 09:29:06 +00:00
Sven Schnelle bf9e9309c0 Lenovo PMH7: add pmh7_ultrabay_power_enable()
Can be used to enable/disable Ultrabay power on Thinkpads
who control that with the PMH7. (i.e. T60)

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 19:47:42 +00:00
Sven Schnelle cf7dffeabc Lenovo H8: add h8_ultrabay_device_present()
returns 1 if a CDROM/HDD device is plugging in the
ultrabay. Return 0 if there's a battery or superio
extensions plugged in.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27 19:47:28 +00:00
Sven Schnelle 4fff74b69f Lenovo PMH7: add pmh7_touchpad_enable()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 19:57:26 +00:00
Sven Schnelle ee4c6f7c80 Lenovo H8 EC: add missing systemstatus.asl include
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17 14:55:21 +00:00
Sven Schnelle 1b9d2ee6ca PMH7: Add dock event control
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17 12:54:32 +00:00
Sven Schnelle 14748a58d9 Lenovo H8 EC: add missing include for thermal.asl
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-13 09:23:45 +00:00
Sven Schnelle 3e2f6790ed Lenovo H8 EC: Set fancontrol to Automatic management
My Notebook gets far to hot without fan, so just enable automatic
fan control by default.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12 18:18:24 +00:00
Sven Schnelle 1fa61ebb33 PMH7: Add chip config
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 19:43:50 +00:00
Sven Schnelle ffcd1439f3 EC: Add Lenovo H8
Move the EC support code from the X60 mainboard to a generic
driver, as this EC is used in many thinkpads. Also move the
ACPI code to this directory for this reason.

This patch also adds a chip config, so that the initial setting
for basic register can be specified in devicetree.cb

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 19:43:32 +00:00
Sven Schnelle f9a0b927f5 ACPI EC: add ec_query function
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15 09:52:07 +00:00
Sven Schnelle 0238a9caa3 ec/acpi: make ACPI register pair configurable
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 08:18:27 +00:00
Sven Schnelle 8d94d7c4a7 ACPI EC: add ec_set_bit() / ec_clr_bit()
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14 08:18:17 +00:00
Uwe Hermann 539500ee33 pmh7.[ch]: Add missing license headers.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-02 23:56:15 +00:00
Sven Schnelle 6f92d21b12 Properly add Lenovo EC to build
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01 19:19:53 +00:00
Sven Schnelle 4a6c9d159c Add support for the Lenovo PMH7 embedded controller
Lenovo PMH7 (Power Management Hardware Hub) is found in
most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-01 10:44:26 +00:00
Stefan Reinauer f13d7f185b Only add EC code if EC is selected in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 23:56:48 +00:00
Sven Schnelle 7592e8bd9c Add new ec subdir for Embedded Controllers and common ACPI EC support
Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
of having their own copies of those functions.

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 11:43:03 +00:00