This file does not exist in the coreboot tree. One should place this
file in the `site-local` subdirectory and specify the paths by means
of `site-local/Kconfig`.
Change-Id: I86ac2a6176947f12194bec6b63bedd7db79820a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This code is identical except for some renaming.
Change-Id: I93795a6087ce0daca27c0d5038a1febd6ca9c775
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This will help reduce duplication and make it easier to add new members
to the cpu_info struct.
BUG=b:194391185, b:179699789
TEST=Compare assembly of romstage and ramstage before and after
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I31f264f4bb8b605fa3cb3bfff0d9bf79224072aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
mb_set_up_early_espi should only be called when
SOC_AMD_COMMON_BLOCK_USE_ESPI is selected.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable CCP DMA use in PSP verstage. This helps to reduce the boot time.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement
in the boot time.
Before CCP DMA:
508:finished loading body 898,286 (287,576)
Total Time: 2,146,182
After CCP DMA:
508:finished loading body 853,627 (240,061)
Total Time: 2,110,117
Cq-Depend: chrome-internal:4116566
Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP verstage can access the boot device either in Programmed I/O mode or
DMA mode. Introduce a boot device driver and use the appropriate mode
based on the SoC support.
BUG=b:194990811
TEST=Build and boot to OS in Guybrush.
Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811.
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.
BUG=b:199822704
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.
BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.
Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Update the DPTF parameters received from the thermal team.
BUG=b:188596619
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clevo indicated that DIMMs running at 2933 MHz are not supported on a
number of processors used for this model.
Change-Id: Iadf611a64de664c783696e51cfe858ca95903936
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Match the behavior of the other TGL-U boards.
Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the
CPU RP and add a TODO.
Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I7255ac1ec6c43dd4b21325ae60e117458bea956d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I375ab879dd95d6a7a20644dc36312a1e62f58226
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I4e5be60d2784d003a388c52254514d0ab4d002b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: Id26d9dfc3822b9120360fc2cb2ced8d67345a659
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Always On Always Connected block is referenced as AOAC in the code,
so add that acronym in the comment and change the "Connect" to
"Connected".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This reverts commit d94f8bbe9d.
This is a reland of https://review.coreboot.org/57651. The original
change broke parallel abuild runs since the xcompile file was deleted by
every recursive call to abuild. This issue was fixed by rebasing on top
of a change which only regenerates the xcompile on non-recursive calls.
BUG=None
TEST=Parallel abuild run succeeds.
Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
`intel_microcode_find()` function uses cached ucode data hence it would
avoid locating ucode.bin from CBFS while passing ucode.bin pointer to
FSP.
Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
guybrush does not have a light sensor, do not include ACPI0008
ACPI device (Light sensor that will be managed by acpi-als IIO
kernel driver).
BUG=b:200823325
TEST=Check on Guybrush360 the sensor is not presented.
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This change config the DRAM speed to 3733 for primus.
BUG=b:200752480
BRANCH=none
TEST=Verified that `dmidecode -t17` shows the correct
configured memory speed
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change replaces the device tree walks with device pointers by
using alias for dptf_policy device.
Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces the device tree walks with device pointers by
using alias for tcss_usb3_port* devices.
Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With use of device pointers, `dev_find_matching_device_on_bus()` is
now unused and hence this change drops the function.
Change-Id: I30fcb2d9932d770ca614cceffb15646ce8256465
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change replaces the device tree walks with device pointers by
using alias for following devices:
1. audio_rt5682
2. xhci0_bt
3. xhci1_bt
4. acp_machine
5. i2c2
Change-Id: I56921ab54716e4d771d9de1a479f191ca5657eba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
AMD Firmware tool allows configuring the directory table level in which
the binaries have to be added. This helps to achieve space and boot time
savings.
BUG=b:195329409
TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of
~75 ms and space savings of ~600 KB per RW section.
Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Due to the vGPIO is not set correctly, without setting those pins for PEG60,
CPU cannot communicate with PCH about the clkreq state.
BUG=b:200886824
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6adf73103ecb02c67d9a199e13d2ead9b8b2276f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
elogtool was setting the timestamp with the wrong value in the month.
This CL fixes that by incrementing the month by one. This is needed
since gmtime() returns the month value starting at 0.
TEST=pytest elogtool_test.py (see next CL in relation chain)
Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
When the entry delay of L0s is less than the entry delay of L1, GL9755
will enter L0s state first. When it exits from L0s state, the time of L1
entry will be reset. Therefore, the conditions for entering L1 state
cannot be met. In order to enter L1 state, L0s needs to be disabled.
BUG=b:195611000
TEST=Verify GL9755 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: If121b5cb534eb32bac8992683c3f0eee8946acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
It took me a while to understand the SMM set up flow. This adds a
clarifying comment.
BUG=b:194391185, b:179699789
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c73e416b8c583cf870e7a29b0bd7dcc99c2f5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
If abuild called itself recursively, the file already exists and we can
spare us one evaluation of all the makefiles per recursive abuild run.
Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Defining defaults for symbols used inside choices is not allowed. Add a
check for this, so we can drop the existent, overly restrictive checks
in the follow-up change.
Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Shelley Chen