Commit Graph

43034 Commits

Author SHA1 Message Date
Raul E Rangel 3af732ada0 soc/amd/common/block/lpc/spi_dma: Yield after completing transaction
There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.

BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:15:27 +00:00
Raul E Rangel 6f3c9018c6 soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers
Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.

BUG=b:179699789
TEST=Boot guybrush with APOB patches.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:15:15 +00:00
Raul E Rangel b29f9d471b lib/thread: Add mutex
We need a way to protect shared resources. Since we are using
cooperative multitasking the mutex implementation is pretty trivial.

BUG=b:179699789
TEST=Verify thread lock and unlock.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56230
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:14:10 +00:00
Raul E Rangel a98d302fe9 x86/smp/spinlock: Disable thread coop when taking spinlock
Switching threads while holding a spinlock can lead to a deadlock. This
happens if you have two thread trying to print to the serial console
because the uart code uses udelay.

BUG=b:179699789
TEST=Boot guybrush and no longer see a deadlock when printing to
console from a second thread.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b929070b7f175965d4f37be693462fef26be052
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-18 15:14:00 +00:00
Raul E Rangel 9ba36abdc5 lib/thread: Rename thread_cooperate and thread_prevent_coop
Renaming them to thread_coop_disable()/thread_coop_enable() makes them
sound like a pair.

BUG=b:179699789
TEST=Boot guybrush to OS

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56357
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:13:50 +00:00
Raul E Rangel be60a0ddb0 lib/thread: Allow nesting thread_cooperate and thread_prevent_coop
This change allows nesting critical sections, and frees the caller from
having to keep track of whether the thread has coop enabled.


BUG=b:179699789
TEST=Boot guybrush with SPI DMA

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56350
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:13:27 +00:00
Raul E Rangel b95369c914 lib/thread: Clean up initialization sequence
idle_thread_init was actually configuring the BSP thread at the end.
We can instead do this in threads_initialize. This now lets us set
initialized after the idle thread has been set up.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56356
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 15:13:00 +00:00
Raul E Rangel d5dca21a95 lib/thread: Add thread_yield helper method
This helper method is just a shorthand for
`thread_yield_microseconds(0)`. I think it makes it clear that we want
to yield a thread without delaying.

BUG=b:179699789
TEST=build test

Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56349
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18 00:25:29 +00:00
Raul E Rangel d373d5d92f soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.

There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.

BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-18 00:24:09 +00:00
Felix Held e6dd5dc4ea soc/amd/common/block/graphics: add GPU PCI ID for Barcelo
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.

BUG=b:193888172

Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 21:33:17 +00:00
Felix Held d5b51beb79 soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.

BUG=b:193888172

Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 21:32:59 +00:00
Meera Ravindranath 81d367feee soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1
Alder Lake supports IGD Opregion version 2.1.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a6f3df185003a4e38faa920f867ace0b97ab2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:48:12 +00:00
Meera Ravindranath 1b8159b3a1 drivers/intel/gma: Support IGD Opregion 2.1
List of changes:
1. Define new configs for Opregion versions.
2. Assign RVDA to relative address of the Opregion buffer
   in case of opregion 2.1+.

BUG=b:190019970
BRANCH=None

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:48:00 +00:00
Lean Sheng Tan 8d4e67da20 soc/intel/elkhartlake: Expose FIVR config to mainboard
Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.

This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 13:47:25 +00:00
Arthur Heymans c78521b376 util/cbfstool: Remove unused pagesize parameter
Change-Id: Ib672ba8ed418b1a76e4a48951eabda6923358e7a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55581
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 13:45:45 +00:00
Frank Wu f3c0adc69a mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.

BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 13:43:47 +00:00
Sridhar Siricilla e836a43713 mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.

BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-17 13:42:56 +00:00
Patrick Georgi 870cbb91ed util/kconfig: Stop trying to make sense of Linux configs
It only leads to missing symbol errors.

Change-Id: Idbce93232ba2b54561abab5b2747c418d6efa92b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-17 13:40:29 +00:00
Subrata Banik 8005642936 soc/intel/common/block: Drop unused `intelblocks/mp_init.h` include
Change-Id: I8621a38214686b359ee0e7cdf7e92154af3cbc81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56381
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 09:51:48 +00:00
Subrata Banik 3b5a47b096 soc/intel/cannonlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I129f169e5dc394a11d8f7b07486cca4894dbec8e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:38 +00:00
Subrata Banik 82f4ca468d soc/intel/elkhartlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Ieb8063116bee59f6f6bf1f6b0b2349ce22bd67bd
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-07-17 09:51:25 +00:00
Subrata Banik 94f94f8fb3 soc/intel/jasperlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Iefc19bc81125f422b8d4fc2f4af60622e7d28c0f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:15 +00:00
Subrata Banik dbb4e4b241 soc/intel/apollolake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I00ebb9a124eb3b8b893c2b176e14773c05851c18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:51:06 +00:00
Subrata Banik 8993e67f0a soc/intel/icelake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I97f4d9715f3205678acca8fcdfb1a62714dfaa53
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17 09:50:56 +00:00
Subrata Banik a4a1e6a9b1 soc/intel/skylake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I2123a081baaf6fd254fe81d64eaeee1e3248dd34
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56371
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 09:50:44 +00:00
Subrata Banik aec071661c soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:32 +00:00
Subrata Banik 87685c5857 soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: Ib62ad6a5381d346011fbc838dcd64b095fccd67b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:23 +00:00
Subrata Banik f427e8028c cpu/intel: Add dedicated file to grow Intel CPUIDs
This patch removes all local `CPUID_` macros from SoC directories and
creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC
users are expected to add any new CPUID support into cpu_ids.h and
include 'cpu/intel/cpu_ids.h' into respective files that look for
`CPUID_` macro.

Note: CPUIDs for HSW, BDW and Quark are still inside the respective
directory.

Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:14 +00:00
Subrata Banik 647a7bb777 soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS
This patch removes leading zero from CPUIDs as below:
0x05065a -> 0x5065a
0x05065b -> 0x5065b

Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-17 09:49:49 +00:00
Felix Singer f7100eb1c9 mb/google/volteer: Deduplicate lockdown config
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.

Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.

Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 00:10:21 +00:00
Felix Singer 5f235b0a3f mb/google/volteer/baseboard: Configure chipset_lockdown separately
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.

Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.

Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17 00:10:08 +00:00
Felix Held ea192f86c9 mb/google/kahlee/Kconfig: add board-specific MAINBOARD_PART_NUMBER
Before the part number for all boards was "Grunt". This patch adds the
correct part number/name for all variants.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16 20:59:56 +00:00
FrankChu a1b5a6295c mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
Redefine GPIO_EC_IN_RW to GPP_F17

BUG=b:193091165
BRANCH=firmware-volteer-13672.B
TEST=verify FAFT firmware_DevMode Pass

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-16 18:07:07 +00:00
Felix Held f1e8e7f148 include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSR
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-16 14:10:07 +00:00
Yu-Ping Wu 1ce645347c mb/google/cherry: Allow payloads to enable USB VBUS
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.

BUG=b:193499785
TEST=emerge-cherry coreboot
BRANCH=none

Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-07-16 04:15:53 +00:00
Maxim Polyakov 9941e5a5e6 ec/kontron/kempld: Add minimal GPIO driver
The patch adds an interface for configuring GPIOs inside the Kontron
CPLD/EC. This allows to statically define the mode for each GPIO pin
in devicetree.cb of the motherboard or carrier board. For example:

chip ec/kontron/kempld
	device gpio 0 on
		register "gpio[0]"  = "KEMPLD_GPIO_INPUT"
		register "gpio[4]"  = "KEMPLD_GPIO_OUTPUT_LOW"
		register "gpio[5]"  = "KEMPLD_GPIO_OUTPUT_HIGH"
		register "gpio[11]" = "KEMPLD_GPIO_DEFAULT"
	end
end

In this case, <device gpio 0>, like all other devices, is not a real
device inside the EC. These definitions are used to understand the EC
resources and systematize configuration options, but if mark this as
<off>, the initialization step will be skipped in the driver code.

Use KEMPLD_GPIO_DEFAULT or skip it in devicetree.cb to not configure
the GPIO and keep the default mode after CPLD reset.

This work is based on code from the drivers/gpio/gpio-kempld.c linux
driver. Tested on Kontron mAL-10 COMe module [1].

[1] CB:54380 , Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e

Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16 04:12:36 +00:00
Raul E Rangel 000138e6c1 lib/thread: Verify threads are initialized before yielding
In hardwaremain.c we call console_init before threads_initialize. Part
of setting up the uart requires calling udelay which then calls
thread_yield_microseconds. Since threads have not been set up, trying to
yield will result in bad things happening. This change guards the thread
methods by making current_thread return NULL if the structures have not
been initialized.

BUG=b:179699789
TEST=Ramstage no longer hangs with serial enabled

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56318
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 21:50:27 +00:00
Julian Schroeder 577e146895 soc/amd/cezanne: add ACPI CPPC support for AMD
This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.

BUG=b:185814875
TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-15 21:39:04 +00:00
Felix Held 82e2f3229e soc/amd/common/block/cpu/mca/mcax: print all MCAX registers
Also move the registers in the order they are in the hardware.

Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 18:17:42 +00:00
Felix Held ae4f0ceb88 soc/amd/common/block/cpu/mca: make building the BERT support conditional
Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.

Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 17:36:51 +00:00
Felix Held bb0af23868 soc/amd/common/block/cpu/mca: commonize mca_check_all_banks
Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.

Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:36:40 +00:00
Felix Held b97f953fcc soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check
This will allow moving mca_check_all_banks to mca_common.c.

Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:04:51 +00:00
Felix Held d1d6479ddf soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count
This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.

Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:04:28 +00:00
Felix Held 5ce2751d6d soc/amd/common/block/cpu/mca: move function prototypes to local header
Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.

Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:03:54 +00:00
Felix Held e84c3f1898 soc/amd/*/mca: factor out common MCA/MCAX check & print functionality
For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.

Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15 17:03:30 +00:00
Felix Held 64077de176 soc/amd/picasso/mca: factor out mca_has_expected_bank_count
To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.

Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:55:47 +00:00
Felix Held a83a58fe62 soc/amd/common/blocks/cpu/mca: factor out common BERT helper functions
Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:55:20 +00:00
Felix Held 2ecf1561b4 soc/amd/*/mca: factor out BERT entry generation to soc/amd/common
Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 16:54:47 +00:00
Maulik V Vaghela 63e34c4d34 soc/intel/alderlake: Add virtual GPIOs for community 1
Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.

TEST=Check register offset to see if programming is correct.

Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:07:20 +00:00
Julius Werner df5062215f drivers: spi_flash: Add Fast Read Dual I/O support
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)

BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15 14:05:34 +00:00