Commit Graph

19872 Commits

Author SHA1 Message Date
Antonello Dettori 0bcd297d93 mainboard/roda/rk9: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/roda/rk9.

Change-Id: I56fec2a2814ee4b91b11f71dbdca1271792cd0e5
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17302
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:57:06 +01:00
Antonello Dettori 63028fd29d mainboard/roda/rk886ex: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/roda/rk886ex.

Change-Id: I2e88adc444dbbde7a4344829d7bd5a6c9e1f7531
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17301
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:56:30 +01:00
Antonello Dettori 8493b25357 mainboard/rca/rm4100: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/rcs/rm4100.

Change-Id: I8b242eefe796cd93337177fc694ea42c57c53f08
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17300
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 16:55:42 +01:00
Kevin Chiu c4943d86b0 mainboard/google/pyro: Set PL1 override to 12000mW
Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:52:16 +01:00
Kevin Chiu 961d6d45a6 google/pyro: Tune i2c frequency to 400 Khz
tune i2c devices clk for pyro:
I2C0: audio da7219
I2C2: TPM H1
I2C3: wacom touchscreen
I2C4: elan touchpad

BUG=chrome-os-partner:58881
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:50:48 +01:00
Kevin Chiu 49ef5aa99b google/pyro: update timing of sdmode toggling
Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.

sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:48:59 +01:00
Kevin Chiu f5fb219f0f mainboard/google/pyro: Configure PERST pin
Configure GPIO 122 as PERST. This is to assert WiFi PERST
during s0ix entry.

BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: Id760251a1b037feb62ec43199a145e407b074769
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10 16:48:22 +01:00
Antonello Dettori 82fcc1afa1 mainboard/kontron/ktqm77: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/kontron/ktqm77.

Change-Id: I47763d1e2bfeee6366ce24b20d874adf7c6f65be
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17299
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-10 00:58:40 +01:00
Furquan Shaikh 06eee265c2 3rdparty/vboot: update to latest master
Require new recovery reason for rec hash space lock failure in RO.

Change-Id: I606d1a1f51a3a4c127b2933f6fb00ba2ec4885fc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 00:57:27 +01:00
Furquan Shaikh 4b2fed50ed antirollback: Sync TPM space indices with vboot library
BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: I27f2e10556214598d479e4a84e8949465e7da7d6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:56:19 +01:00
Furquan Shaikh fb81474aa5 TPM: Add TPM driver files to romstage
This driver is required for reading and updating TPM space for recovery
MRC data hash in romstage.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: I8edb7af13285a7a192e3d55fc6a11cfe12654bf9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17270
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-10 00:56:04 +01:00
Furquan Shaikh 1220589b4f mainboard/google/reef: Add support for RECOVERY_MRC_CACHE
1. Add RECOVERY_MRC_CACHE region to reef FMAP.
2. Implement helper function for getting event for recovery mode with
memory retraining.
3. Select HAS_RECOVERY_MRC_CACHE.

BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified recovery mode behavior with and without memory training
request on reef.

Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17243
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:55:52 +01:00
Furquan Shaikh cab1c01885 mrc: Add support for separate training cache in recovery mode
1. Re-factor MRC cache driver to properly select RW_MRC_CACHE or
RECOVERY_MRC_CACHE based on the boot mode.
 - If normal mode boot, use RW_MRC_CACHE, if available.
 - If recovery mode boot:
    - Retrain memory if RECOVERY_MRC_CACHE not present, or recovery is
    requested explicity with retrain memory request.
    - Use RECOVERY_MRC_CACHE otherwise.
2. Protect RW and RECOVERY mrc caches in recovery and non-recovery boot
modes. Check if both are present under one unified region and protect
that region as a whole. Else try protecting individual regions.
3. Update training data in appropriate cache:
 - Use RW_MRC_CACHE if normal mode.
 - Use RECOVERY_MRC_CACHE if present in recovery mode. Else use
 RW_MRC_CACHE.
4. Add proper debug logs to indicate which training data cache is used
at any point.

BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified that correct cache is used in both normal and recovery
mode on reef.

Change-Id: Ie79737a1450bd1ff71543e44a5a3e16950e70fb3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17242
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:50:23 +01:00
Furquan Shaikh 470852bb08 vboot: Add support for recovery mode with forced memory retraining
1. Add new function vboot_recovery_mode_memory_retrain that indicates if
recovery mode requires memory retraining to be performed.
2. Add helper function get_recovery_mode_retrain_switch to read memory
retrain switch. This is provided as weak function which should be
implemented by mainboard just like {get,clear}_recovery_mode_switch.

BUG=chrome-os-partner:59352
BRANCH=None
TEST=Verified behavior of recovery mode with forced memory retraining on
reef

Change-Id: I46c10fbf25bc100d9f562c36da3ac646c9dae7d1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:44:02 +01:00
Martin Roth 5dc2c1ba8a southbridge/amd: Remove debug echo when building PI
If this information is needed, use make V=1.  That will print the actual
command, not a command that needs to be updated with every addition if
it's going to stay in sync.

Change-Id: I64d33d93c7fad3359d8ef78657bdb86d1fb4d4a1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17328
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:28:09 +01:00
Martin Roth d61b5404dc southbridge/amd: update for amdfwtool size on command line
amdfwtool was getting the ROM size as a #define when it was built.
It has been updated to pass it in as a command line parameter, so
now it can be built just once for abuild as a shared tool.

Update the calls to amdfwtool to pass the ROM size.

All platforms using amdfwtool had the output verified using
a binary compare.

This reverts commit 0529236ed2
(Makefile.inc: Don't share amdfwtool between platforms)

Change-Id: I188b34e08249f2d00bd48957ced750b21f1ec348
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17327
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:27:52 +01:00
Martin Roth 31d95a2eb2 util/amdfwtool: unify return values, verify the file open
- Return an error if the specified file could not be opened. To do this
cleanly, the return value was added.
- Since there's now a unified return value, use it where it makes sense.
- Don't return an error from --help.  If you've asked for usage, it's
not an error.

Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17324
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:26:45 +01:00
Furquan Shaikh 2fe70b69c0 Revert "vboot: Add vboot library to romstage"
This reverts commit 21fdd8d0b2.

I meant to abandon the original change and clicked submit instead.

Change-Id: I1db29b62c5c071113d308583f094f77285c9ba1e
Reviewed-on: https://review.coreboot.org/17346
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 00:26:37 +01:00
Martin Roth 0e94062c2b util/amdfwtool: add usage text
Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17323
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:26:06 +01:00
Martin Roth 8806f7f662 util/amdfwtool: fix clang warnings
Various fixes for clang warnings:

warning: arithmetic on a pointer to void is a GNU extension
- change *rom from void* to char* and cast back to void* as needed

warning: implicit conversion changes signedness
- In ALIGN macro, pass in value as unsigned

warning: no previous prototype for function
- Change functions to static

warning: no previous extern declaration for non-static variable
- Change global variables to static

warning: comparison of integers of different signs
- Make loop variable 'i' unsigned

warning: variable 'output' may be uninitialized
- Make sure an output filename was specified

warning: implicit conversion loses integer precision
- cast fd_stat.st_size to the appropriate type

Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/17322
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:25:45 +01:00
Martin Roth 60f1551461 util/amdfwtool: Update with ROM size command line parameter
Previously, the ROM size was passed into amdfwtool solely as a #define,
meaning that all boards built with the tool would assume the same size
ROM.  This became a problem when the default rom for abuild was updated
to be a board with a 256KB ROM.

The temporary solution was to build amdfwtool individually for each
board that needed it.  This replaces that workaround by allowing the
ROM size to be passed in as a command line parameter.

- Add the -f | --flashsize option to accept a hex value for the ROM
size.
- Add checks to make sure the ROM size supplied is large enough.
- Because the ROM size is not hardcoded, it needs to be passed to
various functions.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615
Reviewed-on: https://review.coreboot.org/17321
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-10 00:24:46 +01:00
Furquan Shaikh 21fdd8d0b2 vboot: Add vboot library to romstage
This library is needed for calculating sha-256 of recovery mrc data in
romstage.

BUG=chrome-os-partner:59355
BRANCH=None
TEST=Compiles succesfully for reef.

Change-Id: Ie257208c7b3ad07d00e4eb777debf19c42a2fc0c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17271
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10 00:07:25 +01:00
Furquan Shaikh 2afc4e7ff7 google/chromeec: Sync ec_commands.h host events with ec codebase
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully for reef

Change-Id: Ibfa5681e16a97e342633104d2aae1fb0402939b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17240
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-11-10 00:07:15 +01:00
Antonello Dettori 9ec1123917 mainboard/kontron/986lcd-m: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/kontron/986lcd-m.

Change-Id: Ib47a4bb3580cb72ee51fb06c6faa6d2d1bd3a80c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-10 00:02:07 +01:00
Antonello Dettori cc026798ce southbridge/intel/i82801dx: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/i82801dx.

Change-Id: I32888930d3742432a73dfc0a32c6586186e6757c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17297
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:48:14 +01:00
Antonello Dettori 35e30f753f mainboard/jetway/j7f2: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/jetway/j7f2.

Change-Id: I37f59f74ac22fbf6e036cdb0515301e8dec400fb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17296
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:48:02 +01:00
Antonello Dettori aa71ee10ec mainboard/iei/pm-lx2-800-r10: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/iei/pm-lx2-800-r10.

Change-Id: I60e5b84141aa4998427c3ecaadf8fce1654b8210
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:47:46 +01:00
Antonello Dettori cca5938ede mainboard/ibase/mb899: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/ibase/mb899.

Change-Id: Id5b460090db58e91b2c210d8633a69114a9c7f6b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17294
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:47:34 +01:00
Antonello Dettori 771d7eccec mainboard/getac/p470: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/getac/p470.

Change-Id: Ifb81976ed7068f9d51edb0d297cd4a12265c51ec
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17293
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:47:26 +01:00
Rizwan Qureshi d8bb69a451 soc/intel/skylake: fix memory access beyond array bounds
chip.h has a config array PcieRpClkReqNumber which corresponds
to a FSP UPD parameter, the size is currently set to 20.
However the size of PcieRpClkReqNumber UPD in FSP2.0 is 24,
so memcpy (config buffer to UPD buffer) in chip_fsp20.c will read
beyond the bounds of config array.
Hence set the size of PcieRpClkReqNumber array based on the FSP in use.

Found-by: Coverity Scan #1365385, #1365386

Change-Id: I937f68ef33f218cd7f9ba5cf3baaec162bca3fc8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/17292
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09 23:29:43 +01:00
Marshall Dawson 1ec0c00179 amd/cpu: Add details to chip names
Newer AMD families have multiple models within them, each often
requiring unique support.  The chip_name files were starting to
have a lot of duplication.  Specify the model in the name, as well
as the family.

Change-Id: I236b260e2a565e212c486347c4a633eadcdf0042
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17187
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:28:52 +01:00
Elyes HAOUAS bb09f285c3 nb/amd/amdmct/mct: Remove commented code
Change-Id: Id0c62cebfceaf083f1bb39514b06b32c55128b85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17172
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:10:00 +01:00
Elyes HAOUAS ec16e9302b mainboard/roda: Use C89 comments style & remove commented code
Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16929
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 23:09:32 +01:00
Elyes HAOUAS 5db945062c nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC
945G-M4 returns : "unknown max. RAM clock (2)",
however, it supports up to DDR2-667MHz.
i945/raminit.c sdram_capabilities_max_supported_memory_frequency()
function returns 667 for case 2.

Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17191
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09 23:09:16 +01:00
Shaunak Saha 40d7a454a2 cpu/intel: Add MSR to support enabling turbo frequency
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO
register allows to determine the ratio limits to be used to limit
frequency.

BUG=chrome-os-partner:58158
BRANCH=None

Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17211
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09 21:02:27 +01:00
Kyösti Mälkki f22b26ad86 AMD binaryPI: Delay ACPI S3 backup until ramstage loader
Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09 20:53:03 +01:00
Kyösti Mälkki 67b34f8cfd AGESA: Delay ACPI S3 backup until ramstage loader
Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15470
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09 20:52:40 +01:00
Kyösti Mälkki 9d6f365643 ACPI S3: Remove HIGH_MEMORY_SAVE where possible
Add implementation to use actual requirements of ramstage size
for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB.

Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP
is selected for the platform. Enable this option for AGESA and binaryPI, other
platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack
in low memory for s3 resume path.

Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-09 20:52:07 +01:00
Aaron Durbin 2c7ad8c8d3 mainboard/google/reef: use common google smbios mainboard version
BUG=chromium:663243

Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09 16:52:18 +01:00
Aaron Durbin 15d2a79a1a vendorcode/google: add common smbios mainboard version support
Provide an option to deliver the mainboard smbios version in the
form of 'rev%d' based on the board_id() value.

BUG=chromium:663243

Change-Id: If0a34935f570612da6e0c950fd7e8f0d92b6984f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-09 16:52:06 +01:00
Aaron Durbin 5577a475fc string.h: only guard snprintf() with __ROMCC__
There's no need to keep the snprintf() declaration hidden
for early stages. romcc is the entity that has issues. Therefore,
be explicit about when to guard snprintf().

BUG=chromium:663243

Change-Id: Ib4d0879e52c3f73c6ca61ab75f672f0003fca71f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17289
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09 16:51:52 +01:00
Janice Li e19c80b7ee google/pyro: Update WACOM touchscreen ACPI _HID
WACOM request to add a new identifier `WCOMNTN2`,
and use that for the board Pyro with all LCD combinations.

BRANCH=master
BUG=chrome-os-partner:58093
TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage
Signed-off-by: Janice Li <janice.li@quantatw.com>
Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307
Reviewed-on: https://review.coreboot.org/17257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09 16:46:10 +01:00
Nico Huber b9cee241b9 ec/acpi: Include ec.c unconditionally in romstage
Dependencies on EC code should be specified at board level and not here.
We can include the file unconditionally in romstage and let the linker
decide if it's needed.

Change-Id: Ie2d1970ac1dd175a9d42651573a88cd866f19cb9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17123
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 10:05:18 +01:00
Arthur Heymans c5d972d073 Move select UDELAY_LAPIC from nb/gm45/Kconfig to cpu/model_1067x/Kconfig
Change-Id: I51cf4f35bf2ea95c8c19ab885e6308535314b0af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17153
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 00:26:56 +01:00
Arthur Heymans 10141c3006 nb/intel/gm45: Use LAPIC udelay instead of custom version
This change may slow down the raminit by maximum 200usec,
but reuses the lapic udelay definition.

Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09 00:26:11 +01:00
Arthur Heymans 3cf2d9caf5 mb/lenovo/t400: use socket mPGA478MN instead of BGA945
The T400 features a socket P (mPGA478MN) and could potentially support
model_6fx CPUs.

Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17155
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08 23:39:50 +01:00
Arthur Heymans 306521b82e cpu/intel/socket_mPGA478MN: Add socket P
This mobile CPU socket supports model_6fx and model_1067x.

Change-Id: Iecd6aae22831de7c3810545f0cb0be9738f96a2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17154
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-11-08 23:39:22 +01:00
Arthur Heymans be91398353 mb/gigabyte/ga-945gcm-s2l: add mainboard
Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.

What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.

What does not work:
* resume from suspend (does not work for d945gclf either).

Quirks:
* The Realtek ethernet card requires a reset which currently also
  hardcodes a MAC adress.

This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.

Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17033
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08 23:38:58 +01:00
Andrey Petrov 4c5b31e567 soc/intel/apollolake: Provide chipset value for ifdtool
Change-Id: I99454a9fca3b677a389bcaf7693ff4e18415c9ad
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17259
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-08 23:12:21 +01:00
Andrey Petrov c4d0f526d4 southbridge/intel: Set chipset in ifdtool invocations
Since IFD format is floating, ifdtool needs to be parameterized with a
chipset it is dealing with. Add -p <chipset> argument to ifdtool
invocations if chipset provides it.

Change-Id: I4fd1783b5d994617912aedcf17adc2a98c97227b
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17258
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08 23:11:45 +01:00