Commit Graph

17111 Commits

Author SHA1 Message Date
Timothy Pearson f7d4f73053 nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Under certain conditions (training abort) BlockRxDqsLock could
remain set in violation of the BKDG.  Ensure BlockRxDqsLock is
reset to 0 after a lane training abort.

Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b
Reviewed-on: https://review.coreboot.org/14144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:30:30 +01:00
Lee Leahy a4d8180913 Documentation: x86 MTRR setup, TempRamExit and MTRR loading
Document how to test TempRamExit and verify the MTRR setup and loading.

TEST=None

Change-Id: I57a604fa139edac4b05453547d3caf185db491e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:12:35 +01:00
Lee Leahy b953d05e60 Documentation/Intel: Add more Galileo Gen2 links
Add datasheet links for the components supporting GPIO.  This includes
I2C I/O ports, I2C PWMs, bus buffers and multiplexers.

TEST=None

Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14114
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:35 +01:00
Lee Leahy e9a6d1a813 Documentation: x86 shadow ROM disable
Add documentation on disabling the SPI flash which is mapped (shadowed)
into the x86 address space at 0x000e0000 - 0x000fffff.

TEST=None

Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14112
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:47:06 +01:00
Lee Leahy d75ed0bfd9 soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing successful display of 0x000ffff0 - 0x000fffff does not match
   the end of the SPI flash.

Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:46:59 +01:00
Lee Leahy 1f1f2c4d38 mainboard/intel/galileo: Enable SPI controllers
Enable the SPI controllers on the Quark SoC.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Load the SPI driver stack
*  Testing is successful when the time is able to be displayed on a
   set of seven-segment displays controlled by a Maxim MAX6950 SPI
   display controller.

Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14109
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 19:44:41 +01:00
Patrick Rudolph 66a98ee967 device/dram/ddr3: fix debug output
Add missing punctuation and align output.
No functionality is changed.

Old logging output:
  Revision: 11
  Type    : b
  Key     : 2
  Banks   : 8
  Capacity: 4 Gb
  Supported voltages: 1.5V
  SDRAM width       : 8
  Bus extension     : 0 bits
  Bus width         : 64
  Optional features : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features  : ASR ext_temp_range
  Thermal sensor    : no
  Standard SDRAM    : yes
  DIMM Rank1 Address bits mirrored!!!
  DIMM Reference card B
  DIMM Manufacturer ID cd04
  DIMM Part number F3-1866C9-8GSR
  XMP Profile 1
  Max DIMMs per channel: 4
  XMP Revision: 1.3
  Requested voltage: 1500 mV

New logging output:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 4 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ASR ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : mirrored
  DIMM Reference card: B
  Manufacturer ID    : cd04
  Part number        : F3-1866C9-8GSR
  XMP Profile        : 1
  Max DIMMs/channel  : 4
  XMP Revision       : 1.3
  Requested voltage  : 1500 mV

Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14083
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 18:31:10 +01:00
Aaron Durbin 57dbbbb596 arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstage
When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage
was not updated. Correct this oversight.

Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14142
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
2016-03-21 14:41:21 +01:00
Martin Roth 57fcae1031 MAINTAINERS: Add maintainers for power8 architecture
Change-Id: I0eedda5f31c2809db7871b81ceb3045b782f9df1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14126
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-21 14:35:05 +01:00
Martin Roth 057ce5fa55 MAINTAINERS: Add maintainer to lint scripts, board status & payloads
Change-Id: I3efd4116da1ffda2dbc768d1a447141d8ec76f81
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 14:32:24 +01:00
Martin Roth ae269c0276 payloads: Add a target to print payload git urls and directories
Being able to fetch this list will allow the jenkins builder to securely
fetch the external payloads so we can start testing payload builds.

Change-Id: I777229216b2f11f0f427cd5f8cfa003da4171a77
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 14:32:02 +01:00
Martin Roth e68a4385d4 payloads/Makefile.inc: Clean up Makefile
- Instead of adding each payload to each common target, create a list
and loop through the list for all of the payloads
- '.phony' doesn't work - the target needs to be uppercase '.PHONY'

Change-Id: I4a7712c94d0f127c2fff8cb8fada4b8132a4ab3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 04:03:24 +01:00
Martin Roth c8ed34075b payloads/external: Rename Makefile.inc to Makefile
These makefiles are not included by anything, so they shouldn't be
named Makefile.inc.  Also, having them all be named 'Makefile' makes
some other consolidation work I'm doing much easier.

Change-Id: I1234539ba6a0a6f47d2eb0c21de3da3607c6b8de
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14130
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21 04:03:16 +01:00
Stefan Reinauer c2b50ace1b coreinfo: Allow numbers in addition to F keys
When using coreinfo on a serial console (at least
with gtkterm, picocom and minicom on Ubuntu 15.10)
you can't send F keys to the payload. Allow 1..9
for F1..F9

Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14065
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18 21:47:46 +01:00
Jacob Laska f3f654ddb9 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table
The previous implementation assumed the CPU physical address size to
be 40 which is not true of all platforms. Use an existing function to
obtain the correct CPU physical address to report in the DMAR ACPI
table.

Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3
Signed-off-by: Jacob Laska <jlaska91@gmail.com>
Reviewed-on: https://review.coreboot.org/14102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-03-18 19:15:25 +01:00
Furquan Shaikh 331ac1b078 mtrr: Define a function for obtaining free var mtrr
Instead of hard-coding var mtrr numbers in code, use this function to
identify the first available variable mtrr. If no such mtrr is
available, the function will return -1.

Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14115
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-18 19:14:52 +01:00
Yidi Lin 39e55209dc google/oak: Enable RAM_CODE_SUPPORT
BRANCH=none
BUG=chrome-os-partner:50820
TEST=check /proc/device-tree/firmware/coreboot/ram-code

Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361
Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332564
Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14104
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18 18:57:17 +01:00
henryc.chen aad2903c9c mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN
When system enters suspend, SPM will pull SRCVOLTEN low to turn off some
power rails. VSRMCA7 should follow this pin to turn on/off the power.

BRANCH=none
BUG=none
TEST=verified on Oak rev5

Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f
Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332345
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14103
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18 18:56:23 +01:00
Patrick Georgi 32154d7b12 build system: Allow overriding the path to the futility binary
Change-Id: I84e68e8407149780769c3e6a1148c175e42d1025
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/14100
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-17 15:38:47 +01:00
Andrey Petrov b4e5c5eb1e cpu/x86: compile earlymtrr.c code for romstage as well
In order to make this work earlymtrr.c needed to be removed
from intel/truxton/romstage.c. It's not a ROMCC board so
there's no reason to be including .c files.

Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16 18:56:19 +01:00
Aaron Durbin 5fa5da1083 cpu/x86/mtrr: remove early_mtrr_* functions
I see no user of any of this code. Remove it.

Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14098
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16 18:56:03 +01:00
Aaron Durbin 264bf0b27e cpu/x86/mtrr: move cache_ramstage() to its only user
The Intel i3100 northbridge code is the only user of
cache_ramstage(). Therefore, place it next to the sole
consumer.

Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14097
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16 18:55:51 +01:00
Stefan Reinauer 94534b3132 libpayload: recreate config files
Add all the default options with:

  for i in configs/*
  do
    cp $i .config
    make savedefconfig
    mv defconfig $i
  done

This also switches to minimal config files instead of the full
configuration files that were previously checked in.

Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-03-16 17:56:32 +01:00
Stefan Reinauer 62af53fe10 coreinfo: Rename libpayload variables
LIBCONFIG_PATH -> LIBPAYLOAD_PATH
LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ

Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14099
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-16 17:55:59 +01:00
huang lin 1129f7f636 rockchip: update make_idb.py
make_idb.py only support RK3288 before, add chip parameter, so we can
support RK3399 either.

Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/13913
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-16 15:24:10 +01:00
Naresh G Solanki 1a1515b949 skylake mainboards: Configure gpio PADRSTCFG to PLTRST
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes
IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get
their logic reset over pltrst and hence configuring PADRSTCFG to
PLTRST to prevent IRQ strom after S3 resume.

BRANCH=glados
BUG=chrome-os-partner:50536
TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed
after S3 resume.

Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68
Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/329453
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331174
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16 15:03:30 +01:00
Patrick Georgi d7f6bd5860 util/nvidia/cbootimage: update to latest master
This includes a fix that allows using cbootimage with paths containing
the "@" sign, which happens sometimes in jenkins configurations.

Change-Id: I83154afa35b6d24449e713e57031b1a93d7ac748
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14090
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16 15:02:50 +01:00
Patrick Georgi db2815ecf4 parade/ps8640: Clean up
Sort out some style issues that were identified by Paul.

Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14064
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16 15:02:46 +01:00
Stefan Reinauer 80547369ea coreinfo: Use tinycurses
When using PDcurses over a serial line, the background of
coreinfo is not properly cleared. Hence use tinycurses, which
was the only option when coreinfo was developed.

Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14067
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-03-15 21:45:26 +01:00
Tobias Diedrich 3385ebe59a pcengines/apu1: Enable USB overcurrent detection.
The two external USB ports and the internal USB header have overcurrent
protection chips with the low-active overcurrent signal connected to the
chipset.

The power-on default for this register disables the software detection
of overcurrent conditions.

After setting the register Linux correctly shows the overcurrent
condition in the kernel log (tested by shorting the 5v and gnd lines on
J14 / the internal USB header):
[ 2015.229921] usb usb1-port3: over-current condition
[ 2015.449925] usb usb1-port4: over-current condition

Simlar for the external ports:
[  256.237916] usb usb1-port1: over-current condition
[  256.458084] usb usb1-port5: over-current condition

Note that each signal is shared between two ports:
usboc0#: External ports (port1/5)
usboc1#: Internal ports (port3/4)

Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/14084
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 21:38:20 +01:00
Patrick Rudolph 8ebb95d0c8 lenovo: add config ONBOARD_VGA_IS_PRIMARY
Fix for the T4xx and T5xx series.
It does not apply to X2xx/X6x series as those have only
one GPU, which is always connected to the display.

The T6x series needs special care not handled with this patch.

Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be
deactivated in case a dedicated GPU is found and active,
leaving the system without a working display.

Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-03-15 21:35:54 +01:00
PH Hsu 740e5ec013 google/oak: add table for 4GB configuration
BRANCH=none
BUG=chrome-os-partner:49229
BUG=chrome-os-partner:50806
TEST=power on to kernel on Oak Rev3 with 4GB dram

Change-Id: I32fa881df12eb9b7f66086904aebde3dd1483fbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275
Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331811
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14089
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 21:34:54 +01:00
PH Hsu 3693d0f94b mediatek/mt8173: Enable 4GB mode
If the system is using 4GB of memory, enable 4GB mode in
the memory controller.

Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275
Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331811
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14088
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 21:34:43 +01:00
Koro Chen 00feb3928f google/oak: Remove EC_SUSPEND_L from AP
This pin is not used anymore since Rev5.

BRANCH=none
BUG=chrome-os-partner:49375
TEST=make and boot on Rev4/5

Change-Id: I3c775eb2b5e05256523bfd8be814e516944a2f90
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a87e3babe28413bd879a2d95d4612a5b6b541419
Original-Change-Id: I87972ff8961309ecdad03639e1b6fac1da119cd7
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/331810
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14087
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 21:34:33 +01:00
Martin Roth 621dd8468f Makefile.inc: Add toupper, tolower, and ws_to_under macros
Add a few additional macros that can be used throughout the coreboot
makefiles.

tolower: returns the value in all lowercase
toupper: returns the value in all uppercase
ws_to_under: returns the value with any whitespace changed to underscores

Change-Id: Icd0e6586481d8f229af0e899e0c94ef7c5c672c3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14093
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15 21:18:28 +01:00
Stefan Reinauer 9125073d2a payloads: Enable building depthcharge as part of the coreboot build
For CHROMEOS builds, depthcharge can be built automatically.
This dependency exists because depthcharge without vboot and subsequent
signing of the image doesn't work very well, and both are keyed to that
flag as well.

Change-Id: Id0195bd3b4e454f382782106d6512469106daac5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/10924
Tested-by: build bot (Jenkins)
2016-03-15 21:18:22 +01:00
Stefan Reinauer 730d47537e x86: Drop CONFIG_COMPILE_IN_DSDT
This option is no longer needed, as FMAP support has been
fully integrated in coreboot

Change-Id: I6121b31bf946532717ba15e12f5c63d2baa95ab2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-15 21:17:14 +01:00
Stefan Reinauer 821844534c libpayload: Move base address, stack and heap size to Kconfig
This will allow more payloads to use the standard linker script
instead of implementing their own.

Change-Id: Ie60120769829f427ceb722109d85859b61dbde31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 20:53:38 +01:00
Stefan Reinauer 347a7529aa libpayload: Make comment into help text
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 20:53:27 +01:00
Stefan Reinauer 805d44f2c7 libpayload: Fix ARM workaround code
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10),
so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised
that this ever worked.

Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14076
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:24:41 +01:00
Stefan Reinauer f0acf47ae1 libpayload: Add comment about ARM64 exception stack
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:24:30 +01:00
Stefan Reinauer 31575f6391 coreinfo: Pretty print RAM addresses
Instead of 500, print 0x00000500 in the ram dump module.

Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14072
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:23:30 +01:00
Stefan Reinauer 1e6b86b8b6 libpayload: Move MEMMAP_RAM_ONLY to generic options
MEMMAP_RAM_ONLY is not an architecture specific option,
hence move it out of the architecture specific menu.

Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:23:11 +01:00
Stefan Reinauer 8fda04449f libpayload: Drop CONFIG_LP_CHROMEOS
This is adding complexity to the code more than it saves
space, plus some of the tables could potentially be interesting
outside of the ChromeOS context.

Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:22:58 +01:00
Stefan Reinauer 96d14ac1c9 libpayload: Unify defconfigs
Bring defconfig and defconfig-tinycurses in sync, so that
defconfig and defconfig-tinycurses only differ in the selection
of the curses implementation.

Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14069
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:22:44 +01:00
Martin Roth 24ae84d260 vendorcode/intel/Kconfig: Add broadwell_de symbol to fix lint
The Kconfig lint tool is complaining because this symbol doesn't
exist.  Create a temporary definition that can be removed when
the chipset is added.

Change-Id: I6a8abffcc91773aae16721ee1f48c4c64bd6b486
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14091
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-15 15:23:40 +01:00
Martin Roth 8ba235e2ac genbuild_h: Fix numeric comparison to remove error
Change the comparison of build_timeless from -eq to =

This was generating an error if BUILD_TIMELESS wasn't set:
util/genbuild_h/genbuild_h.sh: line 27: [: : integer expression expected

This wasn't causing the script to fail, and won't even if 'set -e' is
added to the script because the error happens inside an 'if' clause,
which is specifically excluded from failue on 'set -e'.

Change-Id: I6a4e147ece23e83ee682d72db35be9e5d4088c78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14080
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-14 23:37:12 +01:00
Aaron Durbin 08e920e50d util/cbmem: Scale time stamp values correctly
Commit c49014e (timestamp: add tick frequency to exported table)
refactors the code, but forgets to correctly scale the frequency to
megahertz, where the value is read from sysfs, so that printing time
stamp information shows milliseconds instead of microseconds, as can be
seen on the output `cbmem -t` for the ASRock E350M1 below.

```
   0:1st timestamp                                     515
  10:start of ramstage                                 515 (0)
  30:device enumeration                                515 (0)
  40:device configuration                              610 (94)
  50:device enable                                     614 (4)
  60:device initialization                             624 (9)
  70:device setup done                                 639 (14)
  75:cbmem post                                        844 (205)
  80:write tables                                      844 (0)
  90:load payload                                      849 (4)
  15:starting LZMA decompress (ignore for x86)         849 (0)
  16:finished LZMA decompress (ignore for x86)         869 (20)
  99:selfboot jump                                     869 (0)

Total Time: 350
```

So scale the return value correctly to megahertz, by dividing it with
1000.

```
   0:1st timestamp                                     515,655
  10:start of ramstage                                 515,655 (0)
  30:device enumeration                                515,663 (7)
  40:device configuration                              610,620 (94,957)
  50:device enable                                     614,680 (4,059)
  60:device initialization                             624,618 (9,938)
  70:device setup done                                 639,553 (14,934)
  75:cbmem post                                        844,707 (205,154)
  80:write tables                                      844,710 (2)
  90:load payload                                      849,532 (4,821)
  15:starting LZMA decompress (ignore for x86)         849,655 (123)
  16:finished LZMA decompress (ignore for x86)         869,903 (20,247)
  99:selfboot jump                                     869,922 (19)

Total Time: 354,261
```

Change-Id: Iea032c62487c7946b6194a90268755034c6350df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14086
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-14 21:30:01 +01:00
York Yang 15fca66bf0 vendorcode/intel/fsp1_0: Add Broadwell-DE SoC vendor code
Initial vendor codes to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.

Change-Id: I9262c9d70a58f0c7427f0658948adf080f2f6d8f
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14 18:24:43 +01:00
Ben Gardner 08bfba4f02 intel/fsp_baytrail: Enable LPSS in ACPI mode
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would
result in unusable devices, as the resources were set to 0 and the devices
were disabled.
lpss.c was copied from intel/baytrail with a few minor adjustment for the
different config structure.

ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE
and applying the patch that disables clearing gnvs.
https://review.coreboot.org/#/c/14040/

This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode
set to disable and the devicetree set to default.

Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-14 18:24:10 +01:00