The BOOT_BEEP gpio is used to activate the buffer which
isolates the I2S signals from PCH while doing a beep from depthcharge.
It needs to be lo to deactivate the buffer for audio playback from OS.
BUG=chrome-os-partner:47124
BRANCH=None
TEST=boot depthcharge & test beep with devbeep.
Boot OS and test audio playback.
Change-Id: I047513f6cbe9590820dfe3c369161a157864be97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6
Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319220
Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com>
Original-Tested-by: Michael Rang <michael.rang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch power gates the Kepler module
on skylake kunimitsu board. This is required
to save power since this is consuming over 500mw
of power in all active use cases.
The device can be powered on later by using the
kernel driver as required by setting the
kepler enable gpio high.
BRANCH=None
BUG=chrome-os-partner:45962
TEST=Build and Boot Kunimitsu and check lspci.
The Kepler device should not be listed.
Also power measurement of board should give
approximately 300mW of reduction in power.
Change-Id: I244a23385e20ef1431dc895536c8a47e1f5770d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d4fb7d01f32ac307a351c307b8461628c0e5414
Original-Change-Id: Idafa74d7ff14d67a5b1e635f783efd84b5a7399c
Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302277
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12964
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=chrome-os-partner:46335
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I311cc7d2e70cc52a7e90f3c3c60d422b7b998789
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad9450c342c752f87e3385a2acd5dd79b65cc75f
Original-Change-Id: Ib7b1b40c296fce80d5366bd19e7ff20d7161db95
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316287
Original-Commit-Ready: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12963
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
kunimitsu mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
Kunimitsu does support two audio codec, ADI and MAXIM,
hence use AUDIO_DB_ID to read correct codec and craete
NHLT table, this will also help to load only one amplifier ASL
for machine driver consumption.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted kunimitsu board. Audio worked
with both ADI and MAXIM audio card.
CQ-DEPEND=CL:316352
Change-Id: Ic9b9af83a0229fdf5f1cb019245ae65ad9d2f06c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2db85062d65c5e831da297588aa4abb18d6ed1bb
Original-Change-Id: I3b08f3f23b334799a81cde81a30d6f231cc8583f
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315450
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Make sure the latest & greatest Intel targets actually
build in our build system.
intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards. Leaving that disabled for now.
Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd
Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f
Original-Reviewed-on: https://chromium-review.googlesource.com/316717
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BUG=chrome-os-partner:48292
BRANCH=None
TEST=Boot with the write protect screw in place. Issue
crossystem wpsw_boot. It should show 1.
Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316009
Original-Commit-Ready: Arindam Roy <rarindam@gmail.com>
Original-Tested-by: Arindam Roy <rarindam@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12952
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=None
BUG=None
TEST=Built and boot on kunimitsu. Check for the PL1 value over
sysfs interface
"/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw".
Load the system with Aquarium 1000 Fish, average FPS should be
meeting target 60 with this change.
Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e
Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314416
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/12934
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.
Enable MAINBOARD_HAS_LPC_TPM so that they will build.
Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions. Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime. This should allow one rom to be used for all revisions.
The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues. This
seems like the best way to eliminate the need for that symbol.
Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.
Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.
This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.
BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690
Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Auto-indent did me wrong, and I didn't notice it.
Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12655
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If
used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when
it was used in the C code.
Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12664
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO
were never added to the coreboot codebase when the Rangeley code was
brought in from Sage. These symbols disabled ACPI code that was unused
because it caused dmesg warnings due to conflicts with drivers trying to
claim the same addresses as the ACPI code. Because it could be used on
some other platforms, it was left in instead of being completely
removed.
- Change the Kconfig symbol names to simple #defines in the mainboard
code.
- Add the #defines along with comments to the reference platform.
- Hook everything together in dsdt.asl
- Update new mainboard littleplains the same way.
Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12552
Reviewed-by: David Guckian <david.guckian@intel.com>
Tested-by: build bot (Jenkins)
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0. The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0. On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.
This issue did not affect ACPI interrupt routing.
This is just a workaround, and the root issue still needs to be fixed.
Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0. The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0. On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.
This issue did not affect ACPI interrupt routing.
This is just a workaround, and the root issue still needs to be fixed.
Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12629
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The eagleheights platform had 3 warnings:
The SIO device needs an _ADR object to specify the address in addition
to the operating region.
Not all the paths through the _OSC method returned a value. According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.
dsdt.aml 341: Device(SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 140: Method (_OSC, 4)
Warning 3115 - ^ Not all control paths return a value (_OSC)
dsdt.aml 140: Method (_OSC, 4)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _OSC)
- Remove Kconfig default disabling IASL warnings as errors.
Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12522
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The E38xx legacy uart fires IRQ4, not IRQ3.
PCI based IRQ A is switched from IRQ4 to IRQ3,
to get a working IRQ for the legacy uart.
Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12622
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS
.config file to do the same thing.
Change-Id: I29110a382b7770329ef938876426e571fbbbb339
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12569
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.
BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.
Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updated Micron SPD data to correct values
BUG=none
BRANCH=none
TEST=Tested on FAB 4 with Micron Dimm
CQ-DEPEND=CL:312546
Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735
Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313003
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Changed index 3 to be an exception of the default Rcomp Value
BUG=None
BRANCH=None
TEST=Tested on FAB 4 SKU 1
Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622
Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/12591
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updated Memory IDs and SKU IDs for FAB 4
Updated detection of single/dual channel memory to use SPD Index (Memory ID)
Added spd files for new dimms
Removed boardid.h as it is no longer needed
BUG=None
BRANCH=None
TEST=Tested on FAB4 SKU1 and SKU3
Change-Id: I60403c0e636ea28797d94cff9431af921631323e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4
Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312546
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp
Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
dsdt.aml 1445: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1454: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We've actually got more warnings now than when I first tested IASL
warnings as errors. Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.
- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled! *****
***** Please fix the ASL for this platform. *****
Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section.
This fixes the kconfig warning:
warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects
EC_SOFTWARE_SYNC which has unmet direct dependencies
(MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE)
Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12460
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kernel needs to set Audio IRQ as wake capable.
BUG=chrome-os-partner:47450
BRANCH=NONE
TEST=System wakes up from S0ix by pressing headset buttons.
Change-Id: I0f89d05b4c5449e5e3277dde938d941e4ad8cbea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65bf434f7c7e1662211f9c8bf61eeb4f41bdc675
Original-Change-Id: I7b5b564023044b4458eb0976488018b3226f4c70
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12414
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.
BUG=chrome-os-partner:43491
BRANCH=none
TEST=Build for kunimitsu. Tested wake from touchpad on a reworked kunimitsu board.
Change-Id: I4347be8f7a4552c6b583f0797fab64045aa9792e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c21f3b5df21d96937975dc20ee5e2f83fb3d75e
Original-Change-Id: I76e69bdba81ec22ae67c7cff3a807cea8c54a5b3
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311007
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The family variable was not being set yet for skylake, add this
to the current boards.
BUG=chromium:551715
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec
Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311213
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Up to now the GPIO set up macros for input sets up GPIOs to be
mapped to memory space while macros for outputs sets up GPIOs
to be mapped to legacy io space. This patch adds two additional
macros for legacy output definition and changes the old macros
to memory space mapping.
In addition, the intel/minnowmax mainboard is modified to use
the legacy macros for outputs to ensure this mainboard stays
unchanged in terms of functionality.
TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux.
Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12340
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.
If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.
Therefore, also delete files with just print statements.
Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.
Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7108
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- CACHE_ROM is no longer used in the coreboot code. It was removed in
commit 4337020b (Remove CACHE_ROM.)
- CAR_MIGRATION is also no longer used in coreboot code - it was removed
in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION)
- MARK_GRAPHICS_MEM_WRCOMB was removed in
commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB)
Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12327
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch enables the Fan thermal participant device
in the device tree for thermal active cooling action
for DPTF on SKL-U fan based kunimitsu board.
This patch defines the _ART table in dptf ASL file.
With active cooling policy (_ART), we can control the
fan on/off and speed.
BRANCH=None
BUG=chrome-os-partner:46493
TEST=Built for kunimitsu board. Tested to see that the
thermal devices and the participants are enumerated and
can be seen in the /sys/bus/platform/devices. Also,
checked the FAN type the cooling devices enumerated
in the /sys/class/thermal with sysfs interface.
Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af
Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307028
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12323
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6. Remove the last_boot option from all
affected mainboards to eliminate user confusion.
Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead of having many different arrays for USB configuration,
with each array containing one bit of information, have one
array containing all the information for each port.
This way we can put the basic tuning parameters into a
structure and then define structures for the basic supported
configurations.
The existing port definitions are taken from the Skylake HSIO
tuning guide.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados, verify USB functionality in
all ports.
Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506
Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/306734
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12163
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
