If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This effectively reverts commit 5086ccef
(mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe).
Some Librem 15v3/v4 boards are showing issues with NVMe detection or
booting via SeaBIOS, so revert this until a proper fix can be found.
Test: build / successfully boot Librem 15v4 with problematic NVMe drive.
Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For devices sharing same firmware, there may be few customization based
on SKU ID - for example being clamshell or form factor. On Kukui and
Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send
the information to EC.
BUG=b:161767717
TEST=make -j # builds and boots on Juniper
BRANCH=kukui
Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HDMI DDC GPIOs were configured as NC till now in waddledoo.
This may cause HDMI i2c transfer to break and EDID read will
fail due to wrong configuration
Configuring these GPIOs as NF in coreboot to fix the issue.
BUG=b:160324327
BRANCH=None
TEST=HDMI works on DDI2 onn Type-C port
Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C bus3 frequency and insure it meets I2C spec.
BUG=b:161650117
TEST=flash coreboot to the DUT and actual measured I2C bus3
make sure it meet Spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Update MAINBOARD_PART_NUMBER for TGL variants
- MAINBOARD_PART_NUMBER is reported as FRID on acpi
- This is required for cros_config to differentiate
across TGL variants.
- Mosys uses cros_config to identify TGL variants using
data read from FRID
Bug=none
Test=build and boot coreboot on TGLRVP UP3 hardware
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I11d4ab2a5b6ade6c50988a9fec4d9866fe79d7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Set up a 8-byte I/O range at 0x290-0x297 as PIIX4's generic device 9,
which activates a chip select when this range is accessed.
On the P2B family it connects to the W83781D hardware monitor,
allowing access to it over the ISA bus, just like vendor firmware.
Apparently this does not work on p3b-f, but no ill effects observed
either.
TEST=On p2b-ls lm-sensors can detect chip and get readings over ISA.
Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Variants that select BASE_ASUS_P2B_D will also get
MAX_CPUS==2 below, so this was redundant.
Change-Id: I9048a4821f19d90e1489b09e294d2551941abf10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.
Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This applies what commit 79572e4f32 does
to the devicetree settings of the zork devices.
Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- remove comments (except the GPIO group), because it does not contain
useful information that helps to understand the circuit, which we do
not have;
- remove empty lines between macros;
- use a shorter PAD_CFG_GPI_INT() macro instead of
PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode.
Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Converts bit field macros to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes some bit fields to convert to target macros PAD_CFG_*() macros.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch excludes bit fields that should be ignored [1] in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
/intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the middle of the Great DPTF Refactor of 2020, new volteer variants
were added, but their dptf.asl files are no longer used, so delete them.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.
Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.
Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When RTC failure is detected, send IPMI OEM command to issue CMOS clear.
This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS
clear command by resetting RTC data, erasing RW_VPD (TODO) and add a
SEL, then reboot the system.
Tested=on OCP Delta Lake, after removing RTC battery we can see the above
flow can be executed correctly.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF
method to the kernel. These are contradictory. The ownership of the GPIO
should be mutually exclusive between either the OS or the FW. Since we
have two methods exposed this causes the OS to reset the TS twice. Once
using the _ON method, and once using the GPIO. Additionally the _ON
method is waiting for 20ms after reset while the OS driver uses a 50ms
delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the
OS driver is adding additional padding.
The reference design has a 32ms rise time on the reset line. So without
this patch, the OS tries to reset the TS using the _ON method and it
waits for 20ms. This is not enough time for the reset line to reach
high, let alone account for the FW ready time. The OS driver then tries
to reset the device by toggling the GPIO. It waits 50ms which is still
2ms less than required.
This CL removes the GPIO from being exported in the _CRS so the OS
driver won't try and reset the device. It also increases the reset delay
by 32ms to account for the rise time.
This isn't a complete fix. I think that the slow rise time is causing
some kind of metastability in the TS reset hardware. Using a script to
bind and unbind the TS driver, the TS device becomes unresponsive after
~200 iterations. The only way to reset the device is to power cycle.
The TS power is also not currently controlled by the power resource.
This means that we have no guarantee over when the reset line is
toggled. This will lead to issues while spending and resuming.
BUG=b:160854397
TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+
times.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Earlier versions of Dalboz did not correctly handle HS400. One fix was
to add stitching vias, but these boards did not have them. b/156539551
Another possible fix is to add tuning parameters including drive
strength, but that is still a WIP. b/158959725
This should correct OS load failures in the meantime by running the bus
slower.
BUG=b:158845662
TEST=build, flash, boot sku 0x5a80000c to OS
BRANCH=None
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ
Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at
the same time. Add a delay of 100 ms after disabling the stop GPIO. This
will ensure the required delay is inserted for both reset and stop
disable GPIOs simultaneously.
BUG=b:152936541
TEST=Build and boot the waddledoo mainboard. Ensure that the SiS
Touchscreen is functional.
Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
- Delay after REPORT_EN is disabled - 1ms
- Delay after RESET is asserted - 1ms
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
