Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Other drivers may need to know the coreboot log level hence,
export this function rather than marking it static.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Group all data specific to each notify phase in a struct to avoid
redundant code.
Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Sort includes alphabetically, drop spaces after type casts and unbreak
some long lines that are less than 96 characters long.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When coreboot goes to die because FSP returned an error, log the return
value in the message printed by `die()` or `die_with_post_code()`.
Change-Id: I6b9ea60534a20429f15132007c1f5770760481af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The `pci_dev_disable_bus_master()` function doesn't need to be guarded
with `CONFIG(PC80_SYSTEM)`, so move it out of the guard.
Change-Id: I813e0f72c3c624c73ab9ecbe7512359608ace927
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I20d79d4b42908314dbf7021a67b92e5fd2b79556
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I72c0e0c3968cb2e92b35381691762148f4c270e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I71f22100fe56a8b88321d220f98ac03887ce6bd7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I9b523ebee2d2af8585736588306ca687dfe16003
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ifcdfd9fff197391ca0da083e7f6151c2dffe3374
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5c437ee2d62415f9048a24ad4a517fc33eec3cf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ic9e001721baa7b7df89204eed03375e872c93e28
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Id1bbe7d68d9eace3f54e9decbd02f8b2b50d6867
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ieb6626aeb2023ac27eac8a515cc0e561607f9f62
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I1cfea0491f707052db2fbcee078e2c27c5a306c5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I677770168caa95d95fd7d32cadc15ffae8455e8c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ibd78e1c42d6184127277c1b5dea66150027444fe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Elkhart Lake was hooked up to the FSP repo with commit 79fcadb3c4
(soc/intel/elkhartlake: Use FSP from FSP repo by default) making
these headers obsolete. Thus, drop them.
Change-Id: I2d6a4d4614ae21d5b8e77eceb85baa13e491c2ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
When using the default initial core display clock frequency, Magolor has
a rare stability issue where the startup of Chrome OS in secure mode may
hang. Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommendation avoids this problem.
Depend on CL: https://review.coreboot.org/c/coreboot/+/60009
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for magolor.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I5a0ad2bed79b37775184f0bd0a0ef024900cbe34
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a devicetree setting to configure the CdClock (Core Display Clock)
frequency through a FSP UPD. Because the value for this UPD's default
setting is non-zero and devicetree settings default to 0 if not set,
adapt the devicetree values so that the value for the UPD's default
setting is used when the devicetree setting is zero.
Also update the comment describing the FSP UPD in the header file
FspsUpd.h to match the correct CdClock definition.
BUG=b:206557434
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I917c2f10b130b0cd54f60e2ba98eb971d5ec3c97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Subrata Banik