Commit Graph

50615 Commits

Author SHA1 Message Date
Felix Singer 476fe6ae7e soc/intel/baytrail/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 00:52:05 +00:00
Felix Singer 3e90ce547c mb/google/cyan/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:30 +00:00
Felix Singer 1151088c02 mb/google/skyrim/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:18 +00:00
Felix Singer a006259e6f mb/google/slippy/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I950d776a712a104f2caed614886ce2527028ead7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:51:01 +00:00
Felix Singer 1bb621c002 sio/winbond/w83667hg-a/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I3809880312af4736407e361da53f0424280e43d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:50:42 +00:00
Felix Singer a61e6546f6 mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:50:02 +00:00
Felix Singer 69b48d8231 mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:50 +00:00
Felix Singer c64c9cd5fa mb/aopen/dxplplusu/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:20 +00:00
Felix Singer 4da79a7f25 ec/smsc/mec1308/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I0a419c861e84cd96e8337957dc62a7ca5b981e14
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:49:01 +00:00
Felix Singer 612801d0f8 ec/quanta/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I00a6ece73048209861221cba5f2c7381adfa54b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:46 +00:00
Felix Singer ff6b3af113 ec/google/chromeec/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I2cdb1c9ae3a33bfc72767ff60d8948054d4e151a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:30 +00:00
Felix Singer f45a6c2a50 ec/lenovo/h8/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I1c68816f47aa3ed0ab3bf55d4cfde71d5838d051
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:48:07 +00:00
Felix Singer 2f308d4957 sb/intel/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I94b2e6ecb90a2616e184ae9331c397c75089e373
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:47:52 +00:00
Felix Singer b26e255877 mb/51nb/x210/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:56 +00:00
Felix Singer facf7d077c superio/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ibbecba97dd1628889539c2962dd31964c252c8bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:41 +00:00
Felix Singer 18af706d50 vc/google/chromeos/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: I8b2d97063ba199274c1072ba3a12613162a17ef1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14 00:46:20 +00:00
Felix Singer 52f46525b4 drivers/intel/gma/acpi: Replace Store(a,b) with ASL 2.0 syntax
Replace `Store (a, b)` with `b = a`.

Change-Id: Ifd3a814228df6a399fe1110abf5b5bc18e6fd6d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-14 00:46:03 +00:00
Raul E Rangel 0e9cc44d1b Documentation: Add wake source info to device tree documentation
The device tree documentation was promoting using a GPIO wake event and
a GPE wake event. We should only ever have one. This wasn't actually
causing a problem because the wake bit was set on the `irq` property,
but the IO-APIC can't actually wake the system, so it was a no-op.

This change fixes up the markdown so it's formatted correctly, and also
adds a section explaining what the different wake configurations are.

BUG=b:243700486
TEST=mdformat

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67385
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 18:50:54 +00:00
Martin Roth ae7d8379a5 util/release: Update gerrit_stats script to latest version
This updates a number of things:
- Move the cache directory under the .local directory
- Reformat & clean up with perltidy.  Add the perltidy command line.
- Add username and email aliases to clean up duplicates and unknown
  email addresses.
- Use full length commit IDs
- Collect patch commenters
- Check variables before using them as key values
- Ignore patch submit time, just collect the date
- Get stats about large patches
- Format the output better

Example output:
Statistics from commit c35f281934 to commit f8fbf0917c
Patch, Date, Owner, Author, Submitter, Inserted lines, Deleted lines, Subject, Reviewers, Commenters
"f8fbf0917c722378454b07c2e8ec1a3f87b324ae", 2022/12/10, Frank Chu, Frank Chu, Martin Roth, 22, 1, "mb/google/brya/var/marasov: Change FSP board type to Type3", "Frank Chu, Eric Lai" , "-"
"5778e06771627a5541ca2b137e783f47257f05ec", 2022/12/10, Dinesh Gehlot, Dinesh Gehlot, Subrata Banik, 30, 1, "soc/intel/meteorlake: Drop casts around `soc_read_pmc_base()`", "Kapil Porwal, Elyes Haouas" , "Subrata Banik"
"ed8bdefcdf6c19258febb9931d1e8eb12b958bcc", 2022/12/10, Jamie Ryu, Jamie Ryu, Felix Held, 76, 3, "mb/intel/mtlrvp: Add MTL-P RVP board ids", "Usha P,
Sridhar Siricilla, Eric Lai, Subrata Banik" , "Eric Lai, Subrata Banik, Harsha B R, Angel Pons"

- Total Commits: 985
- Average Commits per day: 17.85
- Total lines added: 61475
- Average lines added per commit: 62.41
- Number of patches adding more than 100 lines: 49
- Average lines added per small commit: 37.82
- Total lines removed: 758022
- Average lines removed per commit: 769.57
- Total difference between added and removed: -696547

=== Authors - Number of commits ===
Author                         ,Ptchs ,Revws , Cmnts , Sbmts , Email                                                , Prcnt, Last commit         ,
Earliest_commit
Elyes Haouas                   ,  126 ,   90 ,    28 ,     0 , ehaouas@noos.fr                                      ,12.79%, 2022/12/10 , 2022/10/17
Arthur Heymans                 ,  107 ,   99 ,    28 ,    40 , arthur@aheymans.xyz                                  ,10.86%, 2022/12/10 , 2022/10/17

=== Authors - Lines added ===
Martin Roth                   ,      10103, 16.434%
Kyösti Mälkki                 ,       6044, 9.832%
Arthur Heymans                ,       3314, 5.391%

=== Authors - Lines removed ===
Arthur Heymans                ,    -741944, 97.879%
Felix Held                    ,      -3031,  0.400%
Kyösti Mälkki                 ,      -1680,  0.222%

=== Reviewers - Number of patches reviewed ===
Angel Pons                    ,    272, 27.614%
Eric Lai                      ,    201, 20.406%
Felix Held                    ,    106, 10.761%

=== Submitters - Number of patches submitted ===
Name                          ,      #,  total%,    Own,    own%,  Other,  other%
Felix Held                    ,    482, 48.934%,     56,  11.62%,    426,  88.38%
Martin Roth                   ,    179, 18.173%,     42,  23.46%,    137,  76.54%
Subrata Banik                 ,     54,  5.482%,     31,  57.41%,     23,  42.59%

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie1694116ab36ca4db25d13935adadca10e50068f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-12-13 18:49:13 +00:00
Fred Reitberger a6514e2b1f soc/amd/morgana: Enable GPP clk req disabling
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 17:43:11 +00:00
Robert Zieba 8ff8937843 util/spd_tools: Format lp5 file to golang standards
This commit formats the lp5.go file according to goland standards.

TEST=Built spd_tools

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If102c90f732efc51a90de6cc0e18c879d56699b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-12-13 17:42:33 +00:00
Jeff Li 3de39fa36f soc/intel/common/block: add definition of GPIO configuration
Add two macros:
 - PAD_CFG_NF_OWNERSHIP()
 - PAD_CFG_GPIO_OWNERSHIP()

to support setting the Host Software Ownership (own) fields.

Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13 17:42:03 +00:00
Felix Held 2557d02eee mb/google/guybrush,skyrim: use gpio.h include everywhere
Now that gpio.h will only include the defines in the IASL case, gpio.h
can be included instead of soc/gpio.h in the files that will be directly
or indirectly included in the DSDT.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 15:23:52 +00:00
Felix Held acf96dfcdc include/gpio: skip everything but soc/gpio.h include in ASM & ACPI cases
When gpio.h gets directly or indirectly included in the DSDT ar an
assembly file, everything but the preprocessor defines for the GPIOs
shouldn't be included to keep IASL or the assembler happy.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I046ed87d3947ba5b1fcd0bdd4cffcda57bc13404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70509
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 15:23:37 +00:00
Elyes Haouas 3cd89a003b vc/eltan/security/mboot/Makefile.inc: Remove path to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: Ie2c4a6c2bb55af56cb6e0b013b1a2ed9baa787ef
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70460
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-13 15:19:58 +00:00
Reka Norman 4ae5873e7f mb/google/nissa/var/nivviks,yaviks: Add DmaProperty for ISH
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on nivviks and yaviks.

BUG=b:259716145
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.

Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ

After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA

Change-Id: Iaddb24580bda77df0c70ff58eb098213f8b509ad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:52:57 +00:00
Reka Norman 6419fbf193 drivers/intel/ish: Allow adding DmaProperty to _DSD
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Allow adding
DmaProperty to the _DSD of the ISH device. This will result in the
kernel marking the device as untrusted.

BUG=b:249846505
TEST=Check SSDT is correct, and kernel detects the DmaProperty and
firmware-name properties.

SSDT entry on yaviks with both add_acpi_dma_property and firmware_name
set in devictree:
    Scope (\_SB.PCI0.ISHB)
    {
        Name (_DSD, Package (0x04)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x01)
            {
                Package (0x02)
                {
                    "firmware-name",
                    "adl_ish_lite.bin"
                }
            },

            ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
            Package (0x01)
            {
                Package (0x02)
                {
                    "DmaProperty",
                    One
                }
            }
        })
    }

Change-Id: Ie1539fc757e72e995e98c3ecf83e705e3bede8c0
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:52:37 +00:00
Fred Reitberger 0423bce8e8 soc/amd/morgana: Update pci int defs
Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:38:06 +00:00
Robert Chen 1cd409f3a8 mb/google/brya/var/lisbon: Add Wifi SAR for lisbon
Add wifi sar for lisbon.

BUG=b:260938760
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: Ia347c4cf56bec971700bb53a5804e36e0bad82fb
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70483
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:37:33 +00:00
Robert Chen b9a59f74f0 mb/google/brya/var/gladios: Add Wifi SAR for gladios
Add wifi sar for gladios.

BUG=b:260950906
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage

Change-Id: I4cd015f17c4ddd28414f51a873ae4afc37863708
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70605
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:37:18 +00:00
Subrata Banik 97a45e6a2a soc/intel/cmn/tcss: Skip sending CONN IPC command during S3 resume
This patch skips sending CONN IPC command to PMC if system is resuming
from S3.

Sending CONN IPC command as part of `tcss_configure_dp_mode()` function
results into ERROR while system is resuming from S3.

Additionally, skip `configure_aux_bias_pads()` during S3 resume.

BUG=b:260984500
TEST=Able to test on Google/Rex.

Without this patch:
[ERROR]  pmc_send_ipc_cmd status: fatal
[ERROR]  Port 1 connect request failed
[SPEW ]  [TCSS] TcssInit() - End

With this patch:
No error seen during S3 resume.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-13 14:36:50 +00:00
Sudheer Kumar Amrabadi 982bf99c89 soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
Tranferring a bit to DC through Skuid to update the regulator
node in order to support pro and non-pro

BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs

Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68385
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:35:51 +00:00
Sudheer Kumar Amrabadi 8139fc4be5 soc/qualcomm/sc7280: Add API to differentiate PRO and NON_PRO SKUs
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid. Modified socinfo_modem_supported() API to utilize
helper functions.

BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:35:21 +00:00
Martin Roth 0110e1abe0 util/genbuild_h: Update printf %d to %s for sh compatability
When printing a date, genbuild_h is printing it as two digits, using
a leading zero if the value is below 10.

The shells like bash, dash, etc don't fully import the numbers 08 and
09 when using the printf conversion specifier %d.  They apparently
interpret the numbers as octal and only import the leading 0, dropping
the 8 or 9. This isn't an issue for 01 to 07, because those are valid
octal numbers, so %d prints them without an issue.  Because 08 and 09
are not valid octal, various shells return different errors:

Example shell returns for 'printf "%d" 08':
 bash: printf: 08: invalid octal number
 dash: printf: 08: not completely converted
 fish: 008: value not completely converted
 yash: printf: `08' is not a valid integer
 sash: printf: 08: not completely converted

To prevent this, just print all of the values as strings.

zsh just seems to ignore the possibility of the value being octal
and prints the value as a single digit 0-9.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I97b6aa74d74379f6bdc1f0fceecc8002cc36ca09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70478
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13 14:34:59 +00:00
Frank Chu 4e37a8dad2 mb/google/brya/var/marasov: Enable PIXA touchpad
Correct touchpad setting to make touchpad function workable.

BUG=b:261393412
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchpad function

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3c816ce4293ae362f0e5c18171f296d42b4307c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70440
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:34:08 +00:00
Elyes Haouas 12149ec0a3 mb/intel/coffeelake_rvp/Makefile.inc: Avoid link to non-existent folder
Found using 'Wmissing-include-dirs' command option.

Change-Id: I178c849d07e61d7a237629f3be1b52d3b4abb513
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:33:12 +00:00
Elyes Haouas 167b7fcdd9 soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:31:41 +00:00
Elyes Haouas 878a99f554 soc/intel/broadwell/early_init.c: Use {read,write}32p()
Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:31:11 +00:00
Elyes Haouas bc849b5459 soc/intel/baytrail/pmutil.c: Use {read,write}32p()
Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:30:07 +00:00
Elyes Haouas f12c2b0837 soc/intel/apollolake/pmutil.c: Use {read,wrire}32p()
Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:29:40 +00:00
Elyes Haouas b988f8aac5 soc/intel/alderlake/bootblock: Use 'false/true' macros
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:28:56 +00:00
Elyes Haouas 347b471901 soc/intel/alderlake/bootblock: Use read32p()
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:27:12 +00:00
Elyes Haouas 50f651baea soc/mediatek/common: Use write32p()
Change-Id: I83707071fe1801322dffad7fc89afaef5617f3c7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-13 14:26:41 +00:00
Elyes Haouas b433470b02 soc/cavium/cn81xx: Use write{32,64}p()
Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13 14:26:23 +00:00
Felix Singer eb99f62456 {drivers,superio}/acpi: Replace ShiftRight(a,b) with ASL 2.0 syntax
Replace `ShiftRight (a, b)` with `a >> b`.

Change-Id: I0751d00186e8dff38e02e7bf7d8ebf5a17514a58
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:17:43 +00:00
Felix Singer 447c399d35 soc/intel/acpi: Replace Multiply(a,b,c) with ASL 2.0 syntax
Replace `Multiply (a, b, c)` with `c = a * b`.

Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:16:44 +00:00
Felix Singer 4bbd807c01 soc/intel/acpi: Replace Subtract(a,b) with ASL 2.0 syntax
Replace `Subtract (a, b)` with `a - b`.

Change-Id: I77028c17dcd7925a392d56488d34090837d660f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:16:04 +00:00
Felix Singer bf1de40853 {soc,superio}/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntax
Replace `Subtract (a, b, c)` with `c = a - b`.

Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:14:15 +00:00
Felix Singer fe33b4cb7c soc/intel/acpi: Replace Add(a,b) with ASL 2.0 syntax
Replace `Add (a, b)` with `a + b`.

Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:13:00 +00:00
Felix Singer e4c30044f2 soc/intel/acpi: Replace Add(a,b,c) with ASL 2.0 syntax
Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where
possible.

Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-12 22:12:13 +00:00