Commit Graph

46007 Commits

Author SHA1 Message Date
Cliff Huang 4bc9ac7c29 soc/intel/common/block/pcie/rtd3: Add PM methods to the device.
Add L23 enter/exit, modPHY power gate, and source clock control methods.
DL23: method for L2/L3 entry.
L23D: method for L2/L3 exit.
PSD0: method for modPHY power gate.
SRCK: method for enabling/disable source clock.
These optional methods are to be used in the device ACPI to construct
flows with root port's power management functions.

Test:
Enable and verify DL23, L23D, PSD0, SRCK methods in ssdt.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I79de76f26c8424b036cb7d2719df68937599ca2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07 14:10:14 +00:00
Karthikeyan Ramasubramanian d5ae3f908a util/spd_tools/spd_gen: Add support for Sabrina SoC
Add support to generate SPD binary for Sabrina SoC. Mainboards using
Sabrina SoC are planning to use LP5 memory technology. Some of the SPD
bytes expected by Sabrina differ from the existing ADL. To start with,
memory training code for Sabrina expects SPD Revision 1.1. More patches
will follow to accommodate additional differences.

BUG=b:211510456
TEST=make -C util/spd_tools.
Generate SPD binaries for the existing memory parts in
lp5/memory_parts.json and observe that SPDs for Sabrina is generated as
a separate set without impacting the ADL mainboards.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07 14:09:52 +00:00
David Wu 65aaccda59 mb/google/brya/var/kano: adjust I2C3 speed
This change adjusts I2C3 speed to lower then 400KHz.

BUG=b:215095284
BRANCH=None
TEST=built and verified adjusted I2C3 speed < 400KHz

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ief6773bc37931a5393b5b1b8beaeda61d235f133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07 14:09:32 +00:00
Kevin Chang ccd0905a23 mb/google/brya/var/{taeko, taeko4es}: Configure Acoustic noise mitigation
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1

BUG=b:201818726
TEST=build FW and system power on.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I881ded944530b21d1c5e306089d32387c9c258b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07 14:09:05 +00:00
Matt DeVillier 84d4ccde79 mb/google/cyan: Fix variant GPIOs
- set GPSE-77 (Maxim jack detect) to NC for variants using Realtek audio
- set GPSW-37 to NC for all variants (not used for LPE audio)
- set GPSW-95 (Realtek jack detect) to NC for variant using Maxim audio
- set GPSE-77 as maskable on variant using Maxim audio, to match mask setting
  for jack detect GPIO on other variants
- set GPSE-81 as maskable on CELES to prevent interrupt storm (likely due to
  change in cherryview pinctrl driver circa kernel v3.18  which no longer masks
  all interrupts at init)

Change-Id: I50d4b3516eba8906042bb8dea768b229afcf11ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07 14:08:52 +00:00
Matt DeVillier 2aef22f6fb mb/google/fizz: update VBT for karma variant
Extracted from firmware image:
bios-karma.ro-11343-22-0.rw-11343-22-0.bin

Change-Id: Ic4165523a9114f748174c272ee206dfea80f4541
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07 14:08:36 +00:00
Chris Wang cf7305f053 mb/google/guybrush/var/dewatt: Add ALC5682I-VS and ALC1019 support
Add ID "AMDI5619" for machine driver to support ALC5682I-VS + ACL1019

combination.

BUG=b:211835769
TEST=Build dewatt, codec is functional with new machine driver.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic6cb3bda7b8f1b96485f7b868200c94e6c720c7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
2022-02-07 14:08:16 +00:00
Raul E Rangel 0d6972fcb2 vc/amd/cezanne: Add support to map UARTs
This will allow coreboot to directly write to the UART controller.

BUG=b:215599230
TEST=Try mapping the uart on guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibd346cec2994e612f2901bb91d572982ce2ed5e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-07 14:07:41 +00:00
Sridhar Siricilla 51c75ac0df soc/intel/common: Define enum cpu_perf_eff_type type for core types
The patch defines enum values for small and big cores and uses them
to indicate the big or small core.

TEST=Verify the build for Brya

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I740984a437da9d0518652f43180faf9b6ed4255e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-07 14:07:30 +00:00
Elyes HAOUAS 6efc7edc13 soc/intel/apollolake: Convert to ASL 2.0
Change-Id: Ieb362b5be05421b6ad2b2a3126c2943b7d55d135
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-07 14:07:12 +00:00
Kangheui Won 168c25b82b mb/google/nissa: Add devicetree
Fill in devicetree for nissa baseboard based on schematics.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
TEST=abuild -a -x -c max -p none -t google/brya -b nereid

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6cd332fd05fde19078ebc4bd2797580abfb76f3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-07 14:06:08 +00:00
Felix Held ad8a2a475e drivers/uart/uart8250reg.h: use shifts in constants
The UART8250_FCR_TRIGGER bits are bits 6 and 7 in the register, so 
rewrite the mask and constants as constants shifted by 6.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0663c1a641355b7bfb59f41479d17117178fb895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-07 14:05:05 +00:00
Felix Held ec4493f88b drivers/uart/uart8250reg.h: use BIT() macro for bit definitions
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib726dd77eaf1a4f8a7d9fbf8ab6d46a7bb1de6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-07 14:04:14 +00:00
Felix Held 5bd6096f82 drivers/uart/uart8250reg.h: remove duplicate bit definitions
UART8250_FCR_RXSR is a redefinition of UART8250_FCR_CLEAR_RCVR,
UART8250_FCR_TXSR a redefinition of UART8250_FCR_CLEAR_XMIT and
UART8250_LCR_BKSE a redefinition of UART8250_LCR_DLAB. None of those
redefinitions are used, so just drop them.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b9edae67180b04ff1c887c5742c07c774fc9c59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-07 14:03:11 +00:00
Felix Held b0789ede5f soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UART
Sabrina is compatible with the common AMD UART block and also with the
DRIVERS_UART_8250MEM_32 driver it selects.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-07 14:02:27 +00:00
Arthur Heymans 409e6fc6b9 configs/i440fx: Build-test PARALLEL_MP
Change-Id: If30d715c5a3b44be2832c96316003dc9d139b53f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59695
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-07 13:48:05 +00:00
Arthur Heymans 16fa339d84 cpu/x86/Makefile.inc: Build smi_trigger on !HAVE_SMI_HANDLER
A lot of soc code requires a definition of apm_control, which
smm/smi_trigger.c provided for !HAVE_SMI_HANDLER, but is not added as
a build target.

Fixes building Q35 without smihandler.

Change-Id: Ie57819b3d169311371a1caca83c9b0c796b46048
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-07 13:47:04 +00:00
Arthur Heymans 2412c81fce cpu/x86/mp_init.c: Rename num_concurrent_stacks
This is just the amount of cpus so rename it for simplicity.

Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07 13:46:42 +00:00
Arthur Heymans 96451a7c6d cpu/x86/smm: Improve smm stack setup
Both the relocation handler and the permanent handler use the same
stacks, so things can be simplified.

Change-Id: I7bdca775550e8280757a6c5a5150a0d638d5fc2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-07 13:46:13 +00:00
Felix Held 0eef54b8be soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMU
Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU
code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 19:00:27 +00:00
Felix Held a4d033a66d nb/amd/pi/00730F01/iommu: call pci_dev_set_resources directly
There is no need to have the iommu_set_resources function which only
calls pci_dev_set_resources, so assign pci_dev_set_resources directly to
the set_resources function pointer field in the iommu_ops struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59c20e61a36fcc11b59d786139b4745ff662e560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 19:00:14 +00:00
Felix Held ddf137f822 nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resource
This comment was added with the AMD family 15h Trinity IOMMU support in
commit 88ebbeb7e2 and looks like a copy of
the comment about the subtractive decode ranges in the LPC device. The
IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this
is also not what the code does. This resource is the MMIO region to
configure the IOMMU instead, so fix the comment in all copies of the
IOMMU support code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 18:59:49 +00:00
Felix Held 70f32bb203 soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIO
Sabrina is compatible with the common AMD ACPIMMIO function block
mapping and access functions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I890375654a9cb1156e481c5586007ac81ab84120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 18:59:27 +00:00
Felix Held 6c170e6b3c soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functions
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses.
Using 16 or 32 bit read accesses will return the data from the first
byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in
only the first byte being written which is both unexpected behavior.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 18:59:11 +00:00
Felix Held e5592d3d99 soc/amd/common/block/acpimmio/print_reset_status: extend bit name table
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05 18:58:48 +00:00
Kyösti Mälkki 9ec7227c9b cpu/x86/lapic: Move LAPIC configuration to MP init
Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().

In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.

Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05 07:59:04 +00:00
Kyösti Mälkki 7261b5ade5 cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER
Leftover from using UDELAY_LAPIC on these platforms.

Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05 07:56:48 +00:00
Kyösti Mälkki 7aea15aa6b cpu/x86/lapic: Fix choice X2APIC_ONLY
When sending self an IPI, some instructions may be processed
before IPI is serviced. Spend some time doing nothing, to
avoid entering a printk() and acquiring console_lock and
dead-locking.

Change-Id: I78070ae91e78c11c3e3aa225e5673d4667d6f7bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05 07:49:21 +00:00
Kyösti Mälkki 710bdc42a5 cpu/x86/lapic: Add lapic_send_ipi_self,others()
This avoids unnecessary passing of APIC ID parameter and
allows some minor optimisation for X2APIC mode.

Change-Id: I0b0c8c39ecd13858cffc91cc781bea52decf67c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05 07:48:18 +00:00
Kyösti Mälkki 0c1158b15d cpu/x86/lapic: Unify some parameter
Change-Id: I790fddea747f5db0536159e6c2ac90ea1da2830e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-05 07:47:55 +00:00
Kyösti Mälkki c8d26c0158 cpu/x86/lapic: Support switching to X2APIC mode
The options X2APIC_ONLY and X2APIC_RUNTIME were already user-visible
choices in menuconfig, but the functionality was not actually provided
except for platforms where FSP presumably enabled X2APIC.

Add the logic and related logging for switching to X2APIC operation.

TEST: qemu-system-x86_64 -M Q35 -accel kvm -bios coreboot.rom -serial
stdio -smp 2

PARALLEL_MP, and either X2APIC_ONLY or X2APIC_RUNTIME, need to be
selected for the build of emulation/qemu-q35.

Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-02-05 07:47:17 +00:00
Kyösti Mälkki ceaf959678 cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available
Even when we're not in X2APIC mode, the information in CPUID
leaf 0xb will be valid if that leaf is implemented on the CPU.

Change-Id: I0f1f46fe5091ebeab6dfb4c7e151150cf495d0cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-05 07:46:50 +00:00
Elyes HAOUAS 2c079fce45 src/ec: Get rid of unnecessary blank line {before,after} brace
Change-Id: I9f7c4bdd9299e686c375aced221a72994ef2d6ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04 20:16:42 +00:00
Tim Wawrzynczak f73e49a784 mb/google/brya: Enable UntrustedDevice wifi property for brask & brya
The CNVi Wifi controller is considered an untrusted device for ChromeOS,
therefore enable the new UntrustedDevice property for the cnvi_wifi
device on all brya & brask boards.

BUG=b:215424986
TEST=dump SSDT on google/redrix, verify it contains the expected
UntrustedDevice property

Change-Id: Ieff6eea0865125a7c0f626e1981dda1c9532ebb1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-04 20:12:44 +00:00
Tim Wawrzynczak 3babc8e12c drivers/wifi/generic: Add support for UntrustedDevice ACPI property
The Linux kernel has the idea of an "untrusted" PCI device, which may
have limited I/O and memory access permissions, depending on which IOMMU
domains it may be a part of.

https://crrev.com/c/3406512 is a backport to the ChromiumOS kernel which
checks for this property.

BUG=b:215424986
TEST=dump SSDT on google/redrix, verify it contains the expected
UntrustedDevice property

Change-Id: I1a02ca7c5f717097ec97cf6373b9e0b81a13e05d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-04 20:12:32 +00:00
Jeff Daly 3623eca525 util/ifdtool: Add additional regions for platforms that support them
Some Intel SoCs such as Denverton support additional SPI regions for
things like Innovation Engine firmware or 10GbE LAN firmwares

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-04 20:11:10 +00:00
Angel Pons 8b94d3e9d9 nb/intel/haswell: Report SMBIOS memory speed in MT/s
The memory speed values in SMBIOS tables are expressed in MT/s, not MHz.
Adjust the reported frequency values accordingly.

Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61504
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-04 20:10:51 +00:00
Felix Held cd8771640f soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA
Sabrina has no SATA controller, so remove the corresponding PIRQ
mapping. This was verified with PPR #57243 Rev 1.53.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 20:10:18 +00:00
Felix Held 75739d3913 soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODO
The common AMD data fabric register access code is valid for Sabrina.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97fb2c6006c09297584845a83342e75058d35713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 20:10:00 +00:00
Felix Held 6f9e4ab059 soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMU
The common AMD SMU code and the common AMD SMN access code that gets
selected by the common SMU code are valid for Sabrina.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 20:09:46 +00:00
Felix Held 716ccb7450 soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOAC
The common AMD FCH AOAC bit definitions and helper functions are correct
for Sabrina.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 20:09:36 +00:00
Anil Kumar c6b65c1a81 soc/intel/alderlake: Enable USB2 port reset message on Type-C ports
This change is added to address the issue of USB3 ports downgrading to
high speed during low power modes and not returning back to super speed.

The patch enables port reset event on USB2 ports. This event is
is passed to USB3 upstream ports to upgrade back to super speed (USB3)
after a downgrade during low power state

BUG=b:193287279
TEST=Built coreboot on Gimble and tested type A pen drive detects as
super speed device

Change-Id: Iabc6f308992bf3868da66f152c6d7b0164e64bea
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04 16:52:28 +00:00
Julius Werner b6cf642732 console: Pass log_state to vtxprintf()
This patch makes a slight change in the way CONSOLE_LOG_FAST and
CONSOLE_LOG_ALL are differentiated, by no longer passing a different
tx_byte() function pointer and instead using the `data` argument to
vtxprintf() to encode the difference. It also passes the message log
level through to the tx_byte() function this way, which will be needed
in the next patch.

Change-Id: I0bba134cd3e70c2032689abac83ff53d7cdf2d7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 16:33:36 +00:00
Felix Held 8e4742d76d soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2C
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also
both the type and version read-only register of the I2C controller
contain identical values.

The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are
defined in the dw_i2c_regs struct in the common Designware I2C code
aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since
common DW I2C code doesn't access those, this is no problem.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 15:23:13 +00:00
Felix Held 6151ff3eae drivers/i2c/designware/dw_i2c: improve CONTROL_SPEED_FS definition
The speed control bits of the Designware I2C controller are bits 1 and 2
in the control register, so the values should be written as number
shifted by the number of the first bit. The resulting constant is
identical.

TEST=Timeless build for amd/chausie results in identical binary

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0881dfcd7703ab6a70a9b1a355d5a93771aebc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 15:23:00 +00:00
Felix Held 3bdbdb77a2 soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V
and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the
existing I2C pad control registers the bit definitions are different, so
add a separate function to configure those pads which however still has
the same function signature and is compatible with same data structs
used for the devicetree settings. PPR #57243 Rev 1.50 was used as a
reference.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04 14:02:27 +00:00
Subrata Banik 6d1db72958 soc/intel/alderlake: Remove `soc_gpio_lock_config()` override function
This patch removes `gpios_to_lock` lists and `soc_gpio_lock_config`
override function from Alder Lake SoC as the required config
(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS) to perform GPIO PAD lock
configuration using SMM is not enabled.

Note: The current assumption is that the responsibility of locking the
sensitive GPIOs (from getting reprogrammed by OS or other SW) remains
with the mainboard.

BUG=b:208827718
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e22e8453b0ec7d34c0f7cb4c17e3336286581c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-04 12:29:17 +00:00
Subrata Banik 2fb232af8b soc/intel/common: Remove GPIO PAD lock config override from mainboard
This patch removes mainboard capability to override GPIO PAD lock
configuration using `mb_gpio_lock_config` override function as the
variant GPIO pad configuration table is now capable of locking GPIO
PADs.

BUG=b:208827718
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-04 12:28:52 +00:00
Subrata Banik 526cc3ed44 soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3    =>  Set CSE device state to D0I3
- heci_set_to_d0i3   =>  Function sets D0I3 for all HECI devices

Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.

As per PCH EDS, the HECI device count for various SoCs are:

ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL                     => 1 (CSE)
SKL/Xeon_SP             => 5 (CSE, IDE-R, KT, CSE2 and CSE3)

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-04 12:23:39 +00:00
Shelley Chen ebd75315b4 Hoglin: Switch to using i2c TPM
Redefine Hoglin to be used for Qualcomm's CRD 3.0 board, which uses
i2c for TPM instead of SPI.  From now on, the Piglin board will be
used for all the Qualcomm reference boards that use SPI for TPM.

BUG=b:206581077
BRANCH=None
TEST=hacked an 8MB image and make sure boots on herobrine board

Change-Id: Ie1d71ec8b01f305c1c8fa815a0fb9b7ee022cc19
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-04 07:36:44 +00:00