The 2nd COM port's base address defaults to 0x2f8. Current software
for this system expects the port at 0x3e8.
Configure COMB to use 0x3e8 instead of 0x2f8.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
The serial number and UUID returned by DMI are retrieved from VPD.
The solution supports a 16 character "serial_number" and a 36 character
"UUID" string.
BUG=N/A
TEST=tested on monolith
Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable use of VPD for monolith. This will be used to store the UUID and
Serial number.
BUG=N/A
TEST=build
Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The monolith board doesn't support the S3 and S4 states because of the
watchdog and failover mechanisms.
Remove S3 and S4 from the available sleepstates.
BUG=N/A
TEST=build
Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=tested using fwts on a facebook monolith.
Found-by: fwts 19.12.00
Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Read the CPU temperature from the EC.
For this board the EC support is limited to reading the CPU temperature
sensor at this moment. Events are not supported.
BUG=N/A
TEST=tested on facebook monolith using acpidbg
The TSR0._TMP method is returning the correct values.
Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies
according to the information in the schematic. The IccMax for these
supplies is lower than the standard supported by the SoC.
BUG=N/A
TEST=build
Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Due to build rules, dummy acpi_tables source files were added in many
mainboards. With commit 1e83e5c61a
("src/arch/x86: Build mainboard acpi_tables source if present"),
the build system will build mainboard acpi_tables only if present. Remove
the dummy/empty/blank acpi_tables source files.
BUG=None
TEST=Build test with some google mainboards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The SDIO device is disabled so remove it from the devicetree.
BUG=N/A
TEST=build
Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HDA controller was disabled because no codec exists on the board.
However, this also disabled audio over HDMI.
To correct this, enable Azalia and the HDA controller in the devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is
expected by some parts of the code.
Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Even if they were corrected, they just rephrase the code.
Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of
the RcompTarget structure. All other structures in these functions use a
fixed value.
Replace RCOMP_TARGET_PARAMS with fixed value.
BUG=N/A
TEST=build
Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an fmd file with a layout that allows configuring the system for
measured boot without enabling verified boot.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cbfstool doesn't support % tag yet while this was in the fmd.
Revert the fmd changes that use the % tag.
BUG=N/A
TEST=build
Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The board is booting Linux and has been briefly tested.
SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.
BUG=N/A
TEST=tested on Facebook Monolith
Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
