Commit Graph

27304 Commits

Author SHA1 Message Date
Tristan Shieh 71d227b108 mediatek: Share GPIO code among similar SOCs
Refactor GPIO code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20 13:50:54 +00:00
Nick Vaccaro ccb62960db mb/google/poppy/variants/nocturne: set nvme to use clk src 3
Latest nocturne architecture uses clk src 3 for nvme.

BUG=b:111514174
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme
nocturne devices are able to recognize the nvme controller.

Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27536
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20 13:50:46 +00:00
Patrick Georgi c430ecec9e libpayload/arm64: Drop unused static array
Fixes build with gcc8.1

Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20 11:06:36 +00:00
Martin Roth 5ef51edd4c mainboard/google/kahlee: Create Liara variant
This is based on the Grunt variant.

BUG=b:111607004
TEST=Build Liara

Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20 04:12:01 +00:00
Martin Roth 5254104b46 mainboard/google/kahlee: Create Aleena variant
This is based on the Grunt variant.

BUG=b:111606874
TEST=Build Aleena

Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20 04:11:50 +00:00
Ronald G. Minnich a8fa25138b write_tables: return a pointer to the table
The write_tables function was void. It is a bit more
useful for loading payloads from the romstage
if it returns a pointer to the table it creates.

Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27537
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20 03:26:46 +00:00
Martin Roth 4a6477ed64 util/gitconfig: Make checkpatch non fatal in pre-commit hook
We don't block commits for failing checkpatch in gerrit, and we
shouldn't block them here.  This allows checkpatch to still run, so
users can see the issues, but won't prevent the commit.

Adds a delay if checkpatch fails so that the issues can be seen.

Change-Id: Ibd4e8bb74e0b02825dcdf16e233a061c4bb43f50
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-19 17:46:49 +00:00
Patrick Rudolph 31fb846c59 ec/lenovo/h8/acpi: Apply state on wake
Implement ACPI S3 resume control to restore the state before entering
sleep.
* Store the requested state wake state for bluetooth and WWAN.
* Add new methods to init the state and apply the requested state on wake.
* Call the new method on all devices.

Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19 16:49:18 +00:00
Patrick Rudolph f281b6d175 ec/lenovo/h8/ssdt: Add UWB ACPI interface
Add ACPI methods GUWB and SUWB for thinkpad_acpi.
Required for power control of the UWB module.

Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19 16:48:19 +00:00
Patrick Rudolph 6b7178aa10 ec/lenovo/h8/ssdt: Add keyboard backlight interface
Add methods MLCG and MLCS for thinkpad_acpi kernel module.
Required for backlight or thinklight control from userspace.

Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19 16:44:15 +00:00
Patrick Rudolph 60eca531df ec/lenovo/h8/acpi: Add WWAN ACPI methods
Implement GWAN and SWAN for thinkpad_acpi kernel module.
Both methods allow power control of the WWAN module.

Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19 16:43:08 +00:00
Arthur Heymans 94d79a338b mb/lenovo/x201: Allow use of libgfxinit
Tested on LVDS (internal), VGA and HDMI (on the dock DP++ connector) output with
both native resolution and textmode.

Change-Id: Ibfcb586d7b4cac7f1d22540bb96c288704a277a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27513
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 16:40:24 +00:00
Arthur Heymans 390fb506cc drivers/intel/gma: Default to LVDS for Internal on NEHALEM
Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not
support eDP, therefore default to LVDS.

Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27512
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 16:26:03 +00:00
Patrick Rudolph d0c6797e79 soc/cavium: Add PCI support
* Add support for secure/unsecure split
* Use MMCONF to access devices in domain0
* Program MSIX vectors to fix a crash in GNU/Linux

Tested on Cavium CN81XX_EVB.

All PCI devices are visible.

Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25750
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 13:57:24 +00:00
Patrick Rudolph 02c0814764 payloads/LinuxBoot: Add ARM64 support
Add support for ARCH=ARM64 and introduce CROSS_COMPILE for all architectures.

* Always compress kernel Image using xz
* Create FIT uImage containing the kernel, initramfs and DTB
* Add ARM64 defconfig for all SoCs

Change-Id: I9a0cc248283432fb2384956ca55e687d4127398c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-19 13:54:24 +00:00
Patrick Rudolph 4e2f95b789 device/pci: Add MSI-X helper functions
Basic PCI MSI-X table helper functions.
Imported from GNU/Linux kernel PCI subsystem.

To be used on Cavium to configure MSI-X tables.

Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26329
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 13:52:28 +00:00
Patrick Rudolph fe98e90671 arch/x86/smbios: Add support for table 38
Add support for SMBIOS table 'IPMI Device Information' and use it on
HP Compaq 8200 Elite SFF.

Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans
for IPMI compatible devices.

Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25386
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 13:50:28 +00:00
Rizwan Qureshi 5348512451 Kconfig: Add config to insert ucode address in second FIT
This config is used to provide the name of a region where a microcode
is located. The address of this will be added as the first entry in
the FIT of the topswap bootblock.

This adds a capability to associate two microcodes for each
of the two bootblocks, this allows for the CPU to boot with different
microcodes with 2 separate bootblocks.

Change-Id: I4ee41d90bae34862aa68c9b8bd69288de1335585
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-19 08:07:49 +00:00
Rizwan Qureshi b082670234 Kconfig: Add config for creating a second bootblock
Intel PCH/Southbridges have feature that it is possible
to have the southbridge/PCH look for the bootblock at a 64K or
128K/256K/512K/1MB (in case of newer SoCs) offset instead of
the usual top of flash.
Add configs to create a second bootblock and configure its size.

Change-Id: I4bbd19c35871891b762a0673f840858d972e129e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19 08:07:12 +00:00
Joel Kitching a302e7f46b cbfstool/add-payload: initialize segment headers to 0
Some types of payload segment headers do not use all fields.
If these unused fields are not initialized to 0, they can
cause problems in other software which consumes payloads.

For example, PAYLOAD_SEGMENT_ENTRY does not use the compression
field.  If it happens to be a non-existent compression type,
the 'cbfstool extract' command fails.

BUG=https://ticket.coreboot.org/issues/170
TEST=cbfstool tianocore.cbfs create -s 2097152 -m x86
     cbfstool tianocore.cbfs add-payload -f UEFIPAYLOAD.fd -n payload -c lzma -v
     xxd tianocore.cbfs | head  # visually inspect compression field for 0

Change-Id: I359ed117ab4154438bac7172aebf608f7a022552
Signed-off-by: kitching@google.com
Reviewed-on: https://review.coreboot.org/27540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-19 07:25:37 +00:00
Martin Roth 202e7d4f3c arch/riscv: Fix makefile to only set flags for riscv
This was updating flags for ALL architectures, not just riscv.
That was bad, and gave us errors, although they weren't fatal for
some reason:
i386-elf-gcc: error: missing argument to '-mcmodel='
i386-elf-gcc: error: missing argument to '-march='
i386-elf-gcc: error: missing argument to '-mabi='

This issue started from commit 5fed693a (riscv: add support for
modifying compiler options)

Add comments to the other 'endif' statements since they're now
surrounded by a global ifeq

Change-Id: Ifa12ad98b04a5ac36148609ccdf46ca427fc5a27
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/27535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18 21:59:52 +00:00
Ronald G. Minnich eeb83b6b53 linux_trampoline: use trampoline RAM for the GDT
The linux trampoline was modifying the existing GDT
to add the 0x10 and 0x18 descriptors for Linux.
This will not work when the existing GDT is in ROM.

Change the code to set up a new GDT in what we know to be
RAM.

Tested by booting a linux payload. The main reason this works
is that Linux almost immediately loads its own GDT and then
segment registers. This GDT is a very temporary bridge.

Note that none of this change used to be necessary; the coreboot
GDT was originally compatible with Linux (ca 2000);
then Linux changed.

Change-Id: I13990052fbfd6a500adab8a2db8f7aead1d24fa6
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18 21:32:26 +00:00
Sumeet Pawnikar ebde659503 mb/google/octopus/variants/baseboard: Udpate CPU critical temp
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
busty workloads like Octane, Aquarium on open yorp board with heat sink,
sometime CPU temperature spikes till 99 degree Celsius and DPTF
initiates system shutdown. With reference to previous APL/reef/coral
platforms, this updates 105 degree Celsius for the CPU critical
temperature trip value to avoid shutdown. This patch also updates power
limit1 value to avoid the abrupt thermal shutdown by DPTF.

BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.

Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-18 20:42:33 +00:00
Simon Glass e577168ae3 mainboard/google/Kahlee: Select low-power mode for WiFi
Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.

Note: This currently does not appear to have any effect on grunt.

BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff

With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1

Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18 20:10:45 +00:00
Simon Glass 82eb80cc8c mainboard/google/kahlee: Enable ASPM on PCI express
We should use active-state power management where possible to reduce
power consumption during normal operation. Enable these options.

Linux does not seem to enable this for AMD, and the Intel code in coreboot
does enable these options.

PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it.

BUG=b:110041917
TEST=boot on grunt, see that WiFi and eMMC still run OK

Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27464
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18 20:10:36 +00:00
Xiang Wang 35da319b72 riscv: add CAR interface
Add an interface to support cache as ram.
Initialize stack pointer for each hart.

Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-18 18:56:10 +00:00
Justin TerAvest 3a1a956286 mb/google/octopus: Create meep variant
This creates a meep variant for octopus.
The devicetree overrides are copied from yorp, otherwise everything
just defaults to baseboard settings.

BUG=b:111543000
TEST=None

Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18 18:52:29 +00:00
Felix Held faca0bc2fa superio/nsc: pass the chip-specific ops struct to pnp_enable_devices
Pass the address of the chip-specific ops struct instead of the one of
the generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.

Change-Id: I0c820254e97e3f80470d148552af06940e147b74
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-18 18:52:12 +00:00
Felix Held b0d868e8fe superio/smsc: pass the chip-specific ops struct to pnp_enable_devices
Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.

Change-Id: I16e485494e448ae02e0a7b9e21b90ddbb1a53a4b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-18 18:51:52 +00:00
Felix Held c40275bce0 superio/ite: pass the chip-specific ops struct to pnp_enable_devices
Pass the address of the chip-specific ops struct instead of the one of the
generic pnp_ops struct to the PNP device enable function.
This allows the removal of the LDN-specific ops overrides which is also done in
this patch.

Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/23006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-18 18:49:40 +00:00
Raul E Rangel 3a59174cf0 security/vboot: fix typo
BUG=none
TEST=none

Change-Id: I7027abee66ccdf9b2d37df60ca7f4dbbbae2f9e4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27517
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18 12:20:13 +00:00
Martin Roth 6d4a060bba what-jenkins-does: Pass V=1 through to abuild
Even though we were setting V=1 in the build, this wasn't getting passed
to abuild, so the builds there didn't have additional debug information.
That made it difficult to debug issues on the builder. This sets the
verbose flag for abuild if V=1 is set.

Change-Id: Id9ec50add9693a6c36ffdb5c78d148d0fc012549
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-18 12:19:46 +00:00
Felix Held 9911d64b9e superio/nuvoton: remove LDN-specific ops overrides
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array

Change-Id: I18345d7cc50a7d46cb15584dfb54df28e8534f81
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-18 11:40:20 +00:00
Arthur Heymans ad417c9c7b mb/lenovo/x201: Add data.vbt file
Extracted from live running Thinkpad X201 with vendor firmware.

Change-Id: Ia33b4c1a2af6f7d460375cc8ea4e404963a72244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18 09:46:26 +00:00
Krzysztof Sywula cdeb41482a soc/intel/common/block: Add WhiskeyLake W0 CPUID
TEST=Boot up with W0 stepping processor.

Change-Id: Ia7bcfd5235e57c70aa3f15d0042da8b16cf7e186
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/27500
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18 07:55:51 +00:00
Philipp Hug 52a022f680 sifive/fu540: add empty sdram init and size functions
Change-Id: I65f900a3277bc8a4a83ebc8883d4a325bd690bf8
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-07-18 07:54:54 +00:00
Raul E Rangel 1b43ad7149 libpayload/generic_hub: Detect port disconnect after reset
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.

BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.

Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 20:38:46 +00:00
Xiang Wang 5fed693a52 riscv: add support for modifying compiler options
Each HART of a SoC like fu540 supports a different ISA. In order for the
coreboot's code can run on each core, need to modify the compile options. 
So add this code.

Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-17 18:09:43 +00:00
Felix Held 745e58a5ee pnp_device: improve readability
Add comments on the ops handling in pnp_enable_devices function and the
pnp_info struct.

Also remove the negation in the check if an LDN-specific override is used.
This patch doesn't change the logic though.

Change-Id: I3e80dbce1f29ee3e95e3b1d71c9b8479561d5c1a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-17 18:06:19 +00:00
Kevin Chiu f17a0df112 soc/amd/stoneyridge: Update ACPI external processor name
update external processor name to match declaration in SSDT.

in SSDT:
Processor (\_PR.P000, 0x00, 0x00000410, 0x06) {}
Processor (\_PR.P001, 0x01, 0x00000000, 0x00) {}

in DSDT:
External (_PR_.CP00, UnknownObj)
External (_PR_.CP01, UnknownObj)

After fix this, ACPI _PSL (Passive List) now can return correct list
of processor objects for thermal passive cooling.

BUG=b:111478152
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I78c838608c78eb7b5e3f8d5c67589e082c756201
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27495
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 18:04:25 +00:00
Philipp Deppenwiese 80961af4b6 security/vboot: Add interface for FSP 2.0 mrc caching
* Move vboot/tpm specific implementation to vboot.
* Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set.
* Preparation for software hash function support, no logic changed.

Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 17:40:33 +00:00
Raul E Rangel d29c81d513 libpayload/xhci: Check noop return code when debugging
Make it obvious that the command has failed.

BUG=b:76831439
TEST=Verified on grunt

Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:30:10 +00:00
Raul E Rangel c534a066d8 libpayload: Add UNKNOWN_SPEED to usb_speed enum
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.

Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.

BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.

Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:23:36 +00:00
Jonathan Neuschäfer e73e81d029 Documentation/mb/sifive: Update TODO list; UART driver has been merged
See 894e3a9ec8 ("drivers/uart: Add a driver for SiFive's UART").

Change-Id: I035c238beba28ecafd296f18c0ccda167126ab94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/27398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17 11:53:32 +00:00
p4block 812a839744 Add VBT data for Gigabyte GA-H61-S2PV
Extracted from the stock UEFI using UEFItool & intelvbttool.

Without it, the kernel complains about the missing VBT table.

Additionally, the invalid oprom signature warning given by i915
is also gone.

Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844
Signed-off-by: Pablo Moyano <42.pablo.ms@gmail.com>
Reviewed-on: https://review.coreboot.org/27482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-17 11:40:51 +00:00
Chen, Ping-chung 51962d3f13 mb/google/atlas: Add MIPI camera ASL files
Atlas has one sensor, create a single endpoint to CIO2. Create power
resource for enabling/disabling camera.

BUG=b:111141128
Branch=None
TEST=Testing on Atlas board

Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d
Signed-off-by: Ping-Chung Chen <ping-chung.chen@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-17 11:40:10 +00:00
Martin Roth 30b7c31547 util/docker: Update coreboot-jenkins-node dockerfile
Because earlier versions of debian set /dev as a standard tmpfs
filesystem, that was a simple place to build.  Now, this has been
changed and /dev isn't a standard tmpfs that will grow to 50% of
memory.  It's a fixed, very small size, and can no longer even be
resized.
Because of this, create a new directory to build in and add it to
/etc/fstab.  Mount it when the container is started.

As long as we're at it, make the other build directories (ccache
and slave-root/workspace) tmpfs as well. The builders we're using now
have plenty of memory, so don't write any of the files to disk.

Update the Makefile to get rid of all references to ccache directory.

Change-Id: I21fd2c4395d7ffb9428172f035991338658cd907
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-17 11:38:55 +00:00
Martin Roth 125506e6fb vendorcode/cavium/include: Make bdk_pop and dpop static
Fix an undefined reference error with GCC 8.1

/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.o: In function `bdk_dram_get_size_mbytes':
/home/coreboot/slave-root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-size.c:198: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk
/libbdk-dram/bdk-dram-test.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-init-ddr3.o: In function `init_octeon3_ddr3_interface':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/bdk/libdram/dram-init-
ddr3.c:7550: undefined reference to `bdk_pop'
/cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/romstage/vendorcode/cavium/bdk/libdram
/dram-l2c.o: In function `bdk_get_num_cores':
/home/coreboot/slave-
root/workspace/Testing_coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal
/bdk-utils.h:164: undefined reference to `bdk_dpop'
make[1]: *** [src/arch/arm64/Makefile.inc:119: /cb-
build/Testing_coreboot.0/CAVIUM_CN8100_SFF_EVB/cbfs/fallback/romstage.debug]
Error 1

Change-Id: Ifcde5476c6f347c0eac7ca44bac88d3fa4017fb7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2018-07-17 11:38:28 +00:00
Patrick Rudolph 780114fb07 cavium/bdk: Poke the watchdog while PCIe init
Prevent a reboot loop due to slow PCIe init.
Poke the watchdog a few times.

Change-Id: I03739d7dbad3072ccf77364fa4caba42c66ac643
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27455
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 08:15:10 +00:00
Patrick Rudolph bb11232210 cavium/bdk: Fix reference clock
Swap 100Mhz and 156Mhz reference clock.
Correct values are taken from __bdk_qlm_sff81xx_set_reference().

Tested on Cavium's cn8100_sff_evb.

Change-Id: I312ce7379b361594249f9f26f4e561ebf57347df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27454
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 08:05:26 +00:00