Commit Graph

27304 Commits

Author SHA1 Message Date
Patrick Rudolph 239e435739 cavium/bdk: Fix possible divide by zero
Fix Coverity CID1393970

Change-Id: I5db6866b8e51eaea201a4c03e59d7d00f4f826e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17 08:05:13 +00:00
Patrick Rudolph 4461613119 cavium/bdk: Fix coverity and remove hardcoded DRAM speed
* Fix CID1393963 (Uninitialized variables)
* Comment in working code
* Remove workaround to limit DDR speed

Change-Id: I96289da43c1018c2fdf9d013ce7f21d7511ba595
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27452
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 08:05:01 +00:00
Patrick Rudolph 2531865f13 cavium/bdk: Read DDR freq from memory controller
The BDK config subsystem can't store values in romstage.
Read frequency from DDR memory controller instead from
BDK config.

Fixes memory info showing always 0 MT/s.

Change-Id: Iaee33e57e27ca182f41be923cf950868f66d3638
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27451
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 08:04:46 +00:00
Patrick Rudolph 06528d97a9 cavium/bdk: Fix possible buffer overrun
Fix Coverity CID1393975

Change-Id: I275cabf55fba464be7bd4c21dfe5826ea554ac84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17 08:04:30 +00:00
Patrick Rudolph de8e68917f bdk: Use Kconfig options instead of getenv()
* Use Kconfig options instead of unusable getenv
* Select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS on CN81XX
* Fix Coverity CID 1393976 (DEADCODE)

Tested on Cavium's cn8100_sff_evb.

Change-Id: Ia16c0161b0e9cf5d06418e46556c0fb45532a5b1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-17 08:04:21 +00:00
Marc Jones 8247f3df67 mainboard/google/kahlee: Don't default backlight on
Keep the backlight off until it is needed.

BUG=b:72694972
TEST=Backlight turns on at ChromeOS splash screen, not prior.

Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17 01:58:04 +00:00
Marc Jones 290c445911 mainboard/google/kahlee: Enable backlight on resume
BUG=b:72694972
TEST=Backlight turns on ChromeOS resume

Change-Id: I452e2ea94b508b137cf52301df5d2d1ad5c9ab70
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17 01:57:49 +00:00
Marc Jones ee03dc2644 mainboard/google/kahlee: Enable backlight in SMI APMC
Enable the backlight in the OS callback to SMI for APMC. This keeps
the backlight off until the OS is ready to display something.

BUG=b:72694972
TEST=Backlight turns on at ChromeOS splash screen

Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17 01:57:34 +00:00
Marc Jones f3dc659516 mainboard/google/kahlee: Add mainboard resume function
Add the mainboard resume function and __weak variant override.

Change-Id: I808734208bd1ce81428771ea203709b53db56cd3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17 01:54:37 +00:00
David Hendricks fce1d38054 mb/facebook/watson: Update IDPROM region in board.fmd
This updates the IDPROM region along with the unused regions.

Change-Id: If73bb8162d3d0733e3bd8561cd5549f2184db2be
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27505
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17 01:18:12 +00:00
Marc Jones 85aec31c14 soc/amd/stoneyridge: Add GPIO functions to SMM
GPIO functions are required by the Grunt SMI handler.

Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16 15:03:59 +00:00
Marc Jones c9ed3ee8d8 soc/amd/stoneyridge: Fix gpio_set function
The gpio_set function was not writing the correct GPIO register
address.

Change-Id: Ib306773ac72505977b606836bbaf3e2067324894
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16 15:03:40 +00:00
Patrick Rudolph 517c4c1563 soc/cavium: Fix overflow before widen
Fix Coverity CID1393974

Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16 14:41:10 +00:00
Patrick Rudolph cff16b6f9d mb/lenovo/x201: Fix EC SSDT
Move the EC under the LPC PCI device to make sure that the SSDT path
matches the DSDT. Matches the behaviour of all other Lenovo devices.

Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16 07:44:54 +00:00
Raul E Rangel 50a2a86832 libpayload: Make libpayload compile using gnu11
This matches coreboot.

BUG=b:76831439
TEST=emerge-grunt libpayload deptcharge chromeos-bootimage
then booted image

Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-16 07:44:03 +00:00
Raul E Rangel 8fdc9162d9 libpayload/xhci: Document struct offsets on xhci_t
This makes it easier to know what offset each register references.

BUG=b:76831439
TEST=none

Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16 07:43:50 +00:00
Kevin Chiu 8aef4f57f8 google/grunt: fix thermal zone CPU temperature report
there are 3 thermal sensors and index is:
0: 1 Charger
1: 1 SOC
2: 0 CPU

it needs to adjust sensor to index 2 to have correct
CPU temperature.

BUG=b:111284412
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16 07:42:40 +00:00
Simon Glass acad6212c8 mainboard/google/kahlee: Add support for Dediprog em100
This device claims to run at 75MHz with dual read, but it is not always
reliable. Add an option to change the SPI flash speed to 16MHz, to avoid
any problems.

BUG=b:111363976
TEST=manually try to get my em100 running (it doesn't yet)

Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16 07:41:51 +00:00
Simon Glass 46255f7ee4 Kconfig: Make the EM100 config option common
This applied to AMD devices as well as Intel, although the mechanism is
different. Move the option to a common place.

BUG=b:111363976
TEST=USE=em100-mode emerge-reef coreboot
See that a message appears:
 * Enabling em100 mode (slow SPI flash)

Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16 07:41:14 +00:00
Ivy Jian 457253cdc6 mb/google/poppy/variants/nami: Use Pantheon VBT
Add new Pantheon sku-id for loading vbt-pantheon.bin

BUG=b:78663963
BRANCH=firmware-nami-10775.B
TEST=Boots to OS and display comes up.
Check the board specific vbt binary loaded.

Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13 16:30:33 +00:00
Patrick Rudolph fb87e413bd cbfstool: Show current FMAP region in print
In case multiple FMAP regions are specified, print the FMAP name.
Useful if VBOOT is enabled and multiple CBFS are printed.

Change-Id: Id6f29ebeda8a9bde6dfe39362e0f2a5e33c86b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26862
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13 14:34:00 +00:00
Pratik Prajapati 7fd1e4b9b1 intel/wifi: Add WGDS ACPI method for Geo Aware SAR
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD

BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.

Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-13 10:42:04 +00:00
Martin Roth 8919ac726b mainboard/google/kahlee: Add more 3 SPD files
BUG=b:111195311
TEST=Build grunt, verify SPDs are present

Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13 03:08:37 +00:00
Ricky Liang 8d0fd5d7d3 mainboard/google/nocturne: Update GPIO_FCAM_PWR_EN
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board
schematics.

Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://review.coreboot.org/27433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-12 17:28:38 +00:00
Patrick Rudolph ded0c77d48 Coverity: Fix CID1393976
Cast to u64 to prevent possible integer overflow.

Change-Id: I5c7d25278db54523242314cba6c85ac2f7a6c1f3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:22:06 +00:00
Patrick Rudolph f4d81e0385 Coverity: Fix CID1393978
Fix a typo.
Only memcpy into target buffer if pointer is not NULL.

Change-Id: I1aa4b2ce1843e53ab6ed2224eaa928fc79ea3b83
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:21:36 +00:00
Patrick Rudolph 679d624fae Coverity: Fix CID1393979
Fix resource leak in dt_set_bin_prop_by_path().

Change-Id: I1c4d7e01b25847a2091ad90d2d70711beae55905
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-12 15:21:10 +00:00
Xiang Wang 3ec008bf40 riscv: add include/arch/smp/ directory
Replicate directory layout from x86 for SMP.

Change-Id: I27aee55f24d96ba9e7d8f2e6653f6c9c5e85c66a
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27355
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12 11:53:30 +00:00
Pratik Prajapati 6e3cc8855b soc/intel/skylake: add a space in printing ME FPF status
This is cosmetic change

Before:
ME: Power Management Event  : Clean global reset
ME: Progress Phase State    : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation   : NO
ME: FPF status               : fused

After:
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : Unknown phase: 0x08 state: 0x10
ME: Power Down Mitigation   : NO
ME: FPF status              : fused

Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-12 11:53:18 +00:00
Elyes HAOUAS a4fc7bef7f nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMs
Change-Id: Ib1f999447b37a1524d589552ea2eec640c2a2c7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-12 11:52:52 +00:00
Frans Hendriks 34510c377e soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optional
Currently thermal event support can not be disabled at board level.
Define and dependent code are placed in same file.

Move define of HAVE_THERM_EVENT_HANDLER to mainboard file.

Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27415
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12 11:52:23 +00:00
Furquan Shaikh a353d054ae mb/google/octopus/variants/yorp: Enable TBMC device
This change enables tablet mode ACPI device for yorp.

BUG=b:111264961
CQ-DEPEND=CL:1132686

Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:59 +00:00
Furquan Shaikh 13367490b0 mb/google/octopus: Enable TBMC device only for phaser
Enabling of TBMC device on AP side requires corresponding support on the
EC side as well. Since not all octopus variants have tablet mode support
enabled, this change enables TBMC device only for phaser.

BUG=b:111264961

Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:51 +00:00
Furquan Shaikh 4d98916721 mb/google/octopus/variants/bip: Enable EC SW sync
This change enables EC SW sync for bip by removing GBB flag selection
for disabling SW sync.

BUG=b:110523189
TEST=Verified that EC SW sync works fine on bip.

Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12 00:39:44 +00:00
li feng 3130a93bfa skylake: Remove "IshEnable"
Remove "IshEnable" from soc_intel_skylake_config since it's not
used anymore.

Enable/disable ISH by checking if ISH device is turned on or not.

Refer to https://review.coreboot.org/#/c/coreboot/+/26485/.

BUG=b:79244403
BRANCH=none
TEST=Built.

Change-Id: I4d2889af118659852431c87cb516fd19b577efc5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11 10:48:12 +00:00
li feng 0738d2a00d mainboard/google/poppy/variants/atlas: config ISH in mainboard side
To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.

Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.

BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.

Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11 10:47:53 +00:00
Weiyi Lu 60e1fcb07f mediatek/mt8183: add PLL and clock init support
Add PLL and clock init code.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Checked with frequency meter in SOC.

Change-Id: I1f561f66bcf12de6a95c2f64eecd9508bd9bb26c
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/27031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:47:09 +00:00
Tristan Shieh 17180af69a mediatek: Share PLL code among similar SOCs
Refactor PLL code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I11f044fbef93d4f5f4388368c510958d2b0ae66c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27305
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:46:45 +00:00
Tristan Shieh bb684e0c8d google/kukui: Update MMU table in romstage and ramstage
In order to get better performance, map dram as cached after dram ready
in romstage.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Need a futher check after dram
     calibration code ready.

Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27304
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:46:25 +00:00
Tristan Shieh 0eb92dfbc7 mediatek/mt8183: Add MMU operation support
Enable MMU in bootblock for performance, link common code to provide
mtk_mmu_after_dram() to update MMU table in romstage after dram ready,
implement mtk_soc_disable_l2c_sram(), and call
mtk_mmu_disable_l2c_sram() to turn off L2C sram in ramstage.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui.

Change-Id: I4e35f8276ca23de7fd13da3515b9f48d944ead32
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:46:09 +00:00
Tristan Shieh c645a5aac4 mediatek: Share MMU operation code among similar SOCs
Refactor MMU operation code which will be reused among similar SOCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11 10:45:48 +00:00
Martin Roth 1a26a30a7f mainboard/google/kahlee: Update existing SPD files
Add an extra space after 8th value on each line to make it easier
to count the values.
Update the empty spd to remove two random 0x80 values.

BUG=None
TEST=None

Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27423
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:45:19 +00:00
Martin Roth cef673759e mainboard/google/kahlee: Add additional SPDs for variants
BUG=b:111079089, b:80375243
TEST=Build grunt, verify that SPDs are included.

Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/27422
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11 10:45:11 +00:00
Xiang Wang 387417be03 riscv: add support to check ISA extension
Add support to check ISA extension for RISC-V.

Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2018-07-11 10:44:08 +00:00
Michał Żygowski 654a45d2ad src/sb/amd/pi/hudson/sd.c: disable SDR50 tuning and set correct clock freq in SD2.0 mode
According to BKDG for AMD Family 16h Models 30h-3Fh Processors
SDR50 tuning should be disabled in 0xA8 register.

Also fix clock frequency setting in 0xA4 for stepping >= A1
which caused reduced performance of SD cards transfer speed
even by half.

Change-Id: I80ca754b0c89e08aa90ff885467c7486a3efb999
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-10 09:53:22 +00:00
Paul Menzel 209a1bf8ca payloads/Kconfig: Put option *None* at the top
As *None* is special and not a payload, it makes sense to put it at the
top. Also, it was at before the latest addition of the FIT payload
choice.

Fixes: a892cde6 (lib: Add FIT payload support)
Change-Id: I52163ea9472308ecbc396012d9912b9617e0c318
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-07-10 09:53:12 +00:00
Patrick Rudolph 88f81af1ef soc/cavium: Add secondary CPU support
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:07:09 +00:00
Patrick Rudolph ae15fec0b8 soc/cavium/cn81xx: Set cntfrq_el0
Set cntfrq_el0 to provide correct timer frequency.

Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25450
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10 07:05:27 +00:00
Patrick Rudolph bbfeb586a6 mb/cavium/cn8100_sff_evb: Be verbose
Print some useful information about the board.

Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25449
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10 07:04:40 +00:00
Patrick Rudolph d0dcf877e4 soc/cavium: Clean uart code
* Only init UART_FOR_CONSOLE
* Allow UART init with zero baudrate.
* Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic.

Tested on CN8100_SFF_EVB.

Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10 07:03:56 +00:00