Commit Graph

36290 Commits

Author SHA1 Message Date
Elyes HAOUAS af56a77915 src: Remove whitespace between 'sizeof' and '('
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:18:16 +00:00
Angel Pons 89739baf53 {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.

Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-26 21:17:50 +00:00
Rob Barnes 4d2db06ab5 util: Remove extra newlines in log messages
Print adds a newline implicitly. Simply remove the extra newlines.

BUG=None
TEST=Build zork, observe build log

Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:16:35 +00:00
Patrick Rudolph 4aea6915a0 arch/x86/smbios: Fix type4 for EDK2
Mark the CPU as enabled and the socket as populated.
EDK2 tests these flags before further reading this structure.

Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:15:34 +00:00
Patrick Rudolph 604295e508 smbios: Add Type19
Implement type 19 by accumulating the DRAM dimm size found in cbmem's
CBMEM_ID_MEMINFO structure. This seems common on x86 where the
address space always starts at 0.

At least EDK2 uses this table in the UI and shows 0 MB DRAM if not
present.

Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-26 21:15:03 +00:00
Peter Lemenkov f04b262710 autoport: Don't initialize already initialized fields in acpi_tables
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. Also add some comments.

See also these commits:

* Commit a76cf28 with Change-Id
  I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables:
Don't initialize already initialized fields").
* Commit 0c52638 with Change-Id
  I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove
thermal.h header").

Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:14:10 +00:00
Elyes HAOUAS a92acecb54 mb/emulation/qemu-i440fx/northbridge.c: Use SMBIOS macros
Change-Id: I0297c8c4008d9e448793c38a3758dced9ede0d7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:13:12 +00:00
Elyes HAOUAS 416644085a arch/x86/smbios.c: Use macro for 'type_detail'
Change-Id: I95c40acb2fb390c50c8d1af9dd44999f9d57c2d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:12:54 +00:00
Elyes HAOUAS 7d964aed3b nb/intel/haswell: Use macro for dimm->bus_width
Change-Id: Ice91a20470c107f7db0ac83301488ae5afed5a8b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:12:39 +00:00
Jan Dabros ffa58cfc12 util/lint: Add lint and checkpatch coverage for tests/ dir
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I8018b75844e630c9ed46c8bc48f2aa1634bf3369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26 21:11:05 +00:00
Anil Kumar b3b13efde6 mb/intel/tglrvp: Update MAINBOARD_PART_NUMBER
- Update MAINBOARD_PART_NUMBER for TGL variants
- MAINBOARD_PART_NUMBER is reported as FRID on acpi
- This is required for cros_config to differentiate
  across TGL variants.
- Mosys uses cros_config to identify TGL variants using
  data read from FRID

Bug=none
Test=build and boot coreboot on TGLRVP UP3 hardware

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I11d4ab2a5b6ade6c50988a9fec4d9866fe79d7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-07-26 21:09:51 +00:00
Keith Hui 5ffb5a76c6 mb/asus/p2b: Enable hardware monitor access via I/O on ISA bus
Set up a 8-byte I/O range at 0x290-0x297 as PIIX4's generic device 9,
which activates a chip select when this range is accessed.

On the P2B family it connects to the W83781D hardware monitor,
allowing access to it over the ISA bus, just like vendor firmware.

Apparently this does not work on p3b-f, but no ill effects observed
either.

TEST=On p2b-ls lm-sensors can detect chip and get readings over ISA.

Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:09:07 +00:00
Keith Hui 55b1dbef3d sb/intel/i82371eb: Add #defines for DEVRESx registers
These will be put to use in a follow-up.

Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:08:53 +00:00
Keith Hui a5a8e0962a sb/intel/i82371eb: Clean up PM register #defines
Remove EIO define. It is unused and means something else,
elsewhere in the tree.

Move PMIOSE bit definition next to PMREGMISC, where it actually
belongs.

Correct a number of bit defines with glaring errors.

Clarify in comments which PM register defines are in PCI config
space are which are in I/O space.

Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:08:43 +00:00
Elyes HAOUAS 7cf47cfda4 src: Remove unneeded space in license header
Change-Id: Iac0f0c3d102a9a900ac168f8be907349d9a3dd42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:07:36 +00:00
Wisley Chen 10be338b52 mb/google/dedede/var/drawcia: Add G2Touch touchscreen support
BUG=b:155002684
TEST=build drawcia, and check touchscreen can work

Change-Id: I29a891e07bb3c1d8ebe17666c18bfcf3bc1c361d
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-26 21:07:01 +00:00
Matt Papageorge be4376c6c6 util/amdfwtool: Add support for EFS SPI values for F17h and F15h
The Embedded Firmware Structure contains various SPI parameters for
the PSP to program. This change adds support to amdfwtool for
populating these values as well specifying SOC Family and Model.

BUG=b:158755102
TEST=Read EFS values at appropriate offsets using a hex editor. Boot
test on Tremblye and Morphius.

Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:06:10 +00:00
John Zhao acdf5fd66e drivers/usb: Avoid NULL pointer dereference
Coverity detects dereferencing pointers that might be "NULL" when
calling acpigen_write_scope and acpigen_write_device. Add sanity
check for both of scope and name to prevent NULL pointer dereference.

Found-by: Coverity CID 1430454
TEST=Built and boot up to kernel on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8ece3831bbd2641ceafbd71b9dc3db7e04a8eae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43449
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:04:51 +00:00
Martin Roth f09b4b6bee soc/amd/common: Refactor and consolidate code for spi base
Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.

This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.

BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:04:25 +00:00
Tim Wawrzynczak 5a1e2d3f63 ec/google/chromeec: Fix loop off-by-one error in DPTF _OSC
The while loop in \_SB.DPTF._OSC accidentally used <= instead of <, so
there was an error indexing into IDSP.

BUG=b:162043345
TEST=verify disassembled ASL, as well as no BIOS bug mentioned in
/var/log/messages

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I08c4152c59cc9eb13386c825aab983681cfa88ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-26 21:04:08 +00:00
Martin Roth 0b6f35d798 soc/amd/picasso: Update postcode value
I accidentally had the same value for two different postcode
entries.  Fix that.

BUG=None
TEST=Watch postcodes in psp_verstage

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id0bf18efc7e79278a21683c11a1084d2a7d97e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:03:41 +00:00
Martin Roth 87fafcaa8b Kconfig: Remove unnecessary choice names
The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:02:55 +00:00
Tim Wawrzynczak 3a658add7d drivers/intel/dptf: Add missing Scope operator for _FIF
Missed one other scope operator in the DPTF cleanup. This one is for the
fan device, and without this fix, the kernel isn't able to properly
control the fan (it gets confused about whether it's ACPI 4+ compatible
or not).

BUG=b:149722146
TEST=verify /sys/class/thermal/cooling_zone0/max_state returns > 1,
and /sys/class/thermal/cooling_zone0/cur_state is writable, and writing
the value of `max_state` causes the fan to spin faster.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7bd83967ace761ddd17eaeae9c25abb0b2cbe413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26 21:02:31 +00:00
Kyösti Mälkki 8d55f167bf mb/asus/p2b: Drop select SMP
Variants that select BASE_ASUS_P2B_D will also get
MAX_CPUS==2 below, so this was redundant.

Change-Id: I9048a4821f19d90e1489b09e294d2551941abf10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:00:46 +00:00
Kyösti Mälkki eb8bfd0828 smp/spinlock: Do not define barrier() globally
It's not stricly related to spinlocks. If defined, a better
location should be found and the name collisions with other
barrier() defined in nb/intel solved.

Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:00:29 +00:00
Kyösti Mälkki 0199d3bd7f arch/x86: Move cpu_relax()
It's not related to spinlocks and the actual implementation
was also guarded by CONFIG(SMP).

With a single call-site in x86-specific code, empty stubs
for other arch are currently not necessary.

Also drop an unused included on a nearby line.

Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:00:13 +00:00
Kyösti Mälkki c731788929 cpu,soc/intel: Drop select SMP
Implicitly selected with MAX_CPUS != 1.

Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 20:59:52 +00:00
Elyes HAOUAS 8dcccea8e4 src: Remove unused 'include <cbmem.h>'
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 20:59:44 +00:00
Elyes HAOUAS 36b569af55 src/include: Remove unused 'include <stdint.h>'
Change-Id: I407474eac9f44f04036af7182714db7fdc4035f1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 20:59:16 +00:00
Kyösti Mälkki f1a18b20bb mb/x/acpi_tables: Do minor cleanup on includes
Change-Id: I7a6ddf95d085490d52e00ade7bac23e8c8849427
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42865
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:59:02 +00:00
Elyes HAOUAS 1d6484a858 nb/intel/sandybridge: Add missing includes
Change-Id: I9d54d0923a595734a84256ddcafb9dae17615cb0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43348
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:58:20 +00:00
Elyes HAOUAS f50b6625d9 src: Remove extra lines in license header
Change-Id: I7378aa7d6156ece3ab3959707a69f45886f86d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:57:18 +00:00
Angel Pons 582472c158 mb/emulation/qemu-aarch64: Fix up license header
Change-Id: I9730680a8359407a2a03dbb7243a6547420e1f39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43856
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:55:34 +00:00
Angel Pons a29f9e51b0 */mb/google/volteer/**/gpio.h: Fix up license header
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.

Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-26 20:55:19 +00:00
Angel Pons a634dab1a6 skylake boards: Factor out copy-pasted PIRQ routes
Put them in common code just in case something depends on the values.

Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:54:32 +00:00
Angel Pons d8f4436005 mb/intel/saddlebrook/devicetree.cb: Use PCH_IRQ* macros
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I6375f97bc2a30beba5882792328f26e0675621cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43867
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:53:23 +00:00
Angel Pons a7d9266832 device/device.h: Add `is_dev_enabled` function
There are many places where we do this. Put it inside an inline function
for convenience reasons.

Change-Id: I5515a52458b6c78c1a723cb08e6471eb9bac9cd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43871
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:44:36 +00:00
Elyes HAOUAS 7cf1f203e9 cpu/intel/model_206ax: Clean up includes
Change-Id: I5dc2e7b327278c281087c7461e62569aab3fe450
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 18:45:21 +00:00
Elyes HAOUAS 6f739184dd src: Remove unused include <cpu/x86/smm.h>
Found using:
diff <(git grep -l '#include <cpu/x86/smm.h>' -- src/) <(git grep -l 'SMM_DEFAULT_BASE\|SMM_DEFAULT_SIZE\|SMM_BASE\|SMM_ENTRY_OFFSET\|SMM_SAVE_STATE_BEGIN\|APM_CNT\|APM_STS\|apm_control\|set_smm_gnvs_ptr\|set_acpi_mode_on_exit\|io_trap_handler\|southbridge_io_trap_handler\|mainboard_io_trap_handler\|southbridge_smi_set_eos\|smm_southbridge_clear_state\|global_smi_enable\|global_smi_enable_no_pwrbtn\|cpu_smi_handler\|northbridge_smi_handler\|southbridge_smi_handler\|mainboard_smi_gpi\|mainboard_smi_apmc\|mainboard_smi_sleep\|smramc_dev\|smramc_reg\|run_smm_relocate\|smm_is_really_enabled\|is_smm_enabled\|smram_open\|smram_close\|smram_lock\|smm_open\|smm_close\|smm_lock\|_binary_smm_start\|_binary_smm_end\|smm_runtime\|smm_module_params\|smm_handler_start\|smm_get_save_state\|smm_handler_t\|smm_loader_params\|smm_setup_relocation_handler\|smm_load_module\|backup_default_smm_area\|restore_default_smm_area\|smm_region\|SMM_SUBREGION_HANDLER\|SMM_SUBREGION_CACHE\|SMM_SUBREGION_CHIPSET\|SMM_SUBREGION_NUM\|smm_subregion\|smm_list_regions' -- src/)|grep '<'

Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 18:45:00 +00:00
Elyes HAOUAS 273c348884 src: Remove unused 'include <cpu/intel/common/common.h>
Found using:
diff <(git grep -l '#include <cpu/intel/common/common.h>' -- src/) <(git grep -l 'set_vmx_and_lock\|set_feature_ctrl_vmx\|set_feature_ctrl_lock\|cppc_config\|cpu_init_cppc_config\|intel_ht_sibling' -- src/) |grep '<'

Change-Id: I4d749a32aa50fa2f005e8496983013977742a99b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42394
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 18:44:43 +00:00
Felix Held e70b259047 mb/google/zork: remove ACPI_FADT_RESET_REGISTER from fadt_flags
This applies what commit 79572e4f32 does
to the devicetree settings of the zork devices.

Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 17:33:28 +00:00
Felix Held f35cbae938 mb/amd/mandolin: add default USB2 PHY tune parameters to devicetree
Change-Id: I4ea2fb83522d8810fe84e0a3f42bf44f2f911461
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 17:08:18 +00:00
Felix Held 3a7389ef10 amd/picasso: rework USB2 PHY tune parameter handling
BUG=b:161923068

Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 17:08:00 +00:00
Felix Singer 4e58ce1535 soc/skylake: Configure SATA options only if SATA is enabled
Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-26 12:53:33 +00:00
Felix Held 1d0154cee0 soc/amd/picasso: don't apply unconfigured USB2 PHY tune parameters
Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.

BUG=b:161923068

Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 17:44:52 +00:00
Angel Pons c4d4b54314 soc/intel/baytrail/southcluster.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:23:25 +00:00
Angel Pons ea07702f62 soc/intel/baytrail/include/soc/irq.h: Add braces
This reduces the differences between Bay Trail and Braswell, and avoids
unlikely but potential bugs regarding missing braces in macros.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:23:16 +00:00
Angel Pons baebe2afc1 soc/intel/baytrail: Simplify pattrs definitions
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:23:09 +00:00
Angel Pons c5bcd28554 soc/intel/baytrail/smm.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:22:52 +00:00
Angel Pons 5bcd35d6a5 soc/intel/baytrail/smihandler.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:22:41 +00:00