Commit Graph

48686 Commits

Author SHA1 Message Date
Felix Singer c5f7055746 mb/lenovo: Integrate W541 into haswell mainboard
Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus,
integrate it into lenovo/haswell and make it a variant.

Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-07-24 22:24:49 +00:00
Felix Singer b5bdd70758 mb/lenovo/haswell: Make INT15 support T440p specific
In preparation to CB:63514, make the INT15 support specific for the
T440p variant since the W541 doesn't support it currently.

Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-24 22:24:24 +00:00
Felix Singer 104b7db894 mb/lenovo/haswell: Hook up variants Makefile
Change-Id: I36091118d98f71dc4141aca4e45858a22d519a9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-24 22:24:13 +00:00
Wonkyu Kim dc445e9230 intel/common/block/ipu: Add MTL IPU device id
TEST=Build mtlrvp and check IPU0 ACPI ojbect from ssdt

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib5c3d455d272af0e753c775a5fd3f19851b7937d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66056
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-24 02:49:38 +00:00
Subrata Banik 684d00db4b mb/google/rex: Add GBB related configs
This patch adds more GBB related configs. Select
`HAS_RECOVERY_MRC_CACHE` config.

Additionally, move VBOOT_LID_SWITCH config under VBOOT config.

TEST=Able to build the Google/Rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-23 20:25:04 +00:00
Nick Vaccaro f0198b65dc mb/google/brya/var/skolas4es: Correct _PLD values
This patch is to denote the correct value of ACPI _PLD for USB ports.

       +----------------+
       |                |
       |     Screen     |
       |                |
       +----------------+
    C2 |                | A0
    C0 | MLB         DB | C1
       |                |
       +----------------+

BUG=b:216490477
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot

Change-Id: I96202b9ac9586975e960d6577d279c995c67f34e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66031
Reviewed-by: Won Chung <wonchung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-23 20:23:43 +00:00
Jeremy Soller 907c85ad48 soc/intel/alderlake: Hide PMC and IOM devices
Hide these ACPI device so Windows does not warn about missing device
drivers.

Change-Id: Iba6cf7a17eefc9f4f247621f6625151f2fd5f3a7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-23 20:22:22 +00:00
Tim Crawford 990d792ac7 mb/system76/tgl-u: Convert galp5 to a variant
Change-Id: I49185352002f6df2f9e9ab9c39d44cc9247b41b5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23 20:04:35 +00:00
Tim Crawford 146caa7e42 mb/system76/tgl-u: Convert darp7 to a variant
Change-Id: I6b3fe8f4acbb5a2f9fca605e07854ebcc3f2a065
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23 20:04:10 +00:00
Tim Crawford 0d27fb8c44 mb/system76/tgl-u: Convert lemp10 to variant setup
Change-Id: I11f2ebb94b0e9a3e2c18c5b2071ccc3e03c16655
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23 20:03:25 +00:00
Felix Singer ff93c93fef soc/intel/cannonlake: Set MAX_CPUS based on the SoC and PCH
Set the default value for MAX_CPUS in the SoC config and drop it from
the mainboards where it is set to those values.

Change-Id: Ib56fdcfe770ef736a2c5e183481d9f9966570e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-23 19:48:56 +00:00
Amanda Huang 4cd1711cc1 mb/google/skyrim/var/skyrim: Add two supported memory parts
Add two memory parts and generate the associated DRAM part ID.

1) Hynix H9JCNNNBK3MLYR-N6E
2) Hynix H58G56AK6BX069

BUG=b:228415394
TEST=none

Change-Id: I0f5ca291e02e209032e2533f4b2d4241b5e62e42
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-07-23 19:47:14 +00:00
Ian Feng 52d0ec25ee mb/google/nissa/var/xivu: Disable WFC and pen garage based on fw_config
Use fw_config Bit 0 and Bit 1 to control:
Bit 0 = 0 --> enable WFC
Bit 0 = 1 --> disable WFC

Bit 1 = 0 --> enable pen garage wake
Bit 1 = 1 --> disable pen garage wake

BUG=b:238045498
TEST=emerge-nissa coreboot chromeos-bootimage

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bc4753bfd16fd460286aa2b3bb5f3341049f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-23 19:18:12 +00:00
Sean Rhodes d86860b84f soc/apollolake: Don't select VBNV_CMOS if VBNV_FLASH is enabled
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If8af4657508f00feff8525b0135c7f73c1959965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-22 21:40:41 +00:00
Sean Rhodes d061c74949 mb/starlabs/lite: Simplify the flash layout
Remove the sections that coreboot doesn't need to know about.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 21:40:03 +00:00
Nick Vaccaro 7710c68e2a mb/google/brya/var/skolas4es: add WFC definitions to fw_config
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.

Possible values for field WFC bits include:
  option WFC_ABSENT             0
  option_WFC_MIPI_OVTI5675      1
  option WFC_MIPI_OVTI8856      2

BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.

Change-Id: If797b79f0d094816eeb3df7bfded06e92e4e6a32
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22 20:52:33 +00:00
Patrick Georgi a284a36535 util/kconfig: Add README.md documenting the uprev procedure
Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-22 19:27:32 +00:00
Kapil Porwal 381c21910a mb/google/rex: Add TPM device to Kconfig and devicetree
Add TPM device for Rex.
Device details:
I2C Controller/Bus = 4
I2C Slave Address = 0x50
GPE = GPE0_DW1_03/GPP_E03

BUG=b:224325352
TEST=Verified in emulator that there is no regression

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 17:07:01 +00:00
Dtrain Hsu 3132a5fb89 Revert "mb/google/brya/var/kinox: Configure TDC current"
This reverts commit 58f68fb0cb.

Reason for revert: ODM thermal team request that change IA/GT TDC
current back to 20A.

BUG=b:237230877
TEST=Build and boot to Chrome OS

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I6a5cfdc18afb6fe43a3d630e5fa3d77c19640fc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.corp-partner.google.com>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-07-22 13:12:21 +00:00
Tarun Tuli d00048fe56 mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID Kconfig
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read
board_id() on rex.

TEST=Verified builds succeed and code is linked

Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22 07:16:33 +00:00
Andy-ld Lu 05c48ec7e9 mb/google/geralt: Add eMMC and SD card configurations
Geralt reference design has both eMMC and SD card interfaces, so we
configure both in mainboard_init() in ramstage.

TEST=boot to kernel using emmc successfully.
BUG=b:236331724

Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I200a065ab96584d824153480e594e19baae97f9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65976
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 04:11:19 +00:00
Andy-ld Lu eb2a111b92 soc/mediatek/mt8188: Add eMMC and SD card configurations
Geralt reference design has both eMMC and SD card interfaces, so we have
to configure both in ramstage.

Implement msdc.c (mass storage device class) to place the eMMC and SD
card drivers.

This implementation is based on chapter 5.9 in MT8188 Functional
Specification.

TEST=boot to kernel using emmc successfully.
BUG=b:236331724

Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.corp-partner.google.com>
Change-Id: I6594c8466a133d3fdb0084716acca8dcf785f94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65975
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 04:10:37 +00:00
Hui Liu ba16e057ad mb/google/geralt: Implement regulator interface
Control regulator more easily with regulator interface.

TEST=measure 3.0V in VMCH and VMC.
BUG=b:236331724

Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 04:02:49 +00:00
Jack Rosenthal 15e4c0a23f mb/google/brya/var/ghost: Split ghost4adl into 3 variants
We plan to make 3 firmwares which differ only by Kconfig options and
can share a common variant directory.

ghost4adl: Board with an ADL chip.
ghost4es:  Board near identical but has RPL-ES chip.
ghost:     Will have final RPL silicon.

Since they will only differ by Kconfig options and Intel binary blobs,
let's not duplicate the variant directory but instead share it in
common.

BUG=b:239456576
BRANCH=firmware-brya-14505.B
TEST="make menuconfig", verify layout of board selection

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-07-22 03:25:10 +00:00
Raihow Shi a8a6738631 mb/google/brask/variants/moli: set customized_leds for RTL8111K
Follow the LED modification request in ADL_Moli_SC_MB_2022_0601.pdf and
set the customized_leds to 0x0482 based on 7.4 Customizable LED Configuration in "REALTEK+RTL8111K-CG+SPEC+0116" for RTL8111K in moli.

BUG=b:218985167
TEST=emerge-brask coreboot and check RTL8111K LED behaviour

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia154d15ecf14b32a4d589abf27b9573693339a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65958
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 03:22:09 +00:00
Nick Vaccaro 912fea6547 mb/google/brya/var/brya0: add WFC definitions to fw_config
Reserve bits 15 and 16 in the fw_config to be used to specify WFC
population status.

Possible values for field WFC bits include:
  option WFC_ABSENT		0
  option_WFC_MIPI_OVTI5675	1
  option WFC_MIPI_OVTI8856	2

BUG=b:239613517
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot' and make sure it compiles successfully.

Change-Id: I23bdaf7feaff2e6a4979c3da789ab877e6ac3af2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-22 03:20:14 +00:00
Matt DeVillier (AMD) 7f7f65cfb9 mb/google/kahlee: Increase VRAM from 16 to 32 MiB
While adequate for ChromeOS, 16MiB VRAM is insufficient for current
mainline Linux and Windows amdgpu drivers to operate properly. Under
Linux, the driver fails to allocate a framebuffer and causes multiple
kernel panics. Under Windows, the driver fails to load due to
insufficient resources available. Revert the VRAM allocation to the
previous amount of 32MiB.

This change reverts
commit 87dcd0061a ("mainboard/google/kahlee: Reduce VRAM to 16MB")

Test: build/boot Linux 5.17.x on google/liara, verify framebuffer
allocation succeeds and no kernel panic reported.

Change-Id: I1967a203fed80456a20af00943eba21bc1c0577b
Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66022
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22 02:34:52 +00:00
Tim Wawrzynczak c38347873e mb/google/brya/acpi: Poll more frequently in GPPL
The full dGPU power-on sequence, when executed from ACPI, is taking
roughly 15ms or so, which puts it close to the maximum of 20ms required
from the Nvidia spec. Changing the polling period to 100 us instead of 1
ms drastically reduces the time required for this sequence, now taking
typically 7 ms or so. This gives a lot more margin during the power on
sequence.

BUG=b:238466724
TEST=Sequence verified by EE on a scope

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ba676c5fac983a0c1ad1d60c3863d06ed33fa27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66020
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-22 02:20:18 +00:00
Shelley Chen 2a59875694 herobrine: Create Zoglin variant
Zoglin is like Hoglin, but with a smaller flash size, which requires
us to create a new variant.

BUG=b:239851866
BRANCH=None
TEST=Make sure BOARD_GOOGLE_ZOGLIN builds

Change-Id: Id1401a052061dcfc1d1ee41b88ce4a11fd9f3d01
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-22 00:14:39 +00:00
Nick Vaccaro 72b8462a9f mb/google/brya/var/baseboard/skolas: set BOARD_ROMSIZE_KB_32768
Skolas baseboard needs to set BOARD_ROMSIZE_KB_32768, so this change
sets it.

BUG=b:239628052
BRANCH=firmware-brya-14505.B
TEST="emerge-brya coreboot" and verify that the following configs
are set as:
  CONFIG_BOARD_ROMSIZE_KB_32768=y
  CONFIG_COREBOOT_ROMSIZE_KB_32768=y
  CONFIG_COREBOOT_ROMSIZE_KB=32768
  CONFIG_ROM_SIZE=0x02000000

Change-Id: I0846b8e69c8b65e010eef9a8f4a88606197cd0c6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-21 23:02:40 +00:00
Matt DeVillier (AMD) 0303d690c4 MAINTAINERS: Add myself (Matt DeVillier) as a maintainer for all AMD SoCs
Change-Id: I16b3a3b01b54c7bb779f13a76bbd45bee1c864f7
Signed-off-by: Matt DeVillier (AMD) <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66029
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 23:00:13 +00:00
Sean Rhodes 04fc601e04 Documentation: Add the coreboot logo in SVG format
Add the white hare coreboot logo in Documentation so that it can be
used for various things, including the bootsplash for edk2.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3a1d64cc3bf695f88e163eda96e03b841ad04a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65931
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 10:35:16 +00:00
Rex-BC Chen c5d4d964f1 mb/google: Use boolean type for "enable" argument for regulator
Because 0 and 1 are the only possible values,
1. Change input argument "enable" of mainboard_enable_regulator to bool.
2. Change return value of mainboard_regulator_is_enabled() to bool.

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 10:33:22 +00:00
Rex-BC Chen d5dafb2c0a mb/google: Replace some strings in regulator.c
From comments of CB:65875, we replace *_vol to *_voltage.

s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/
s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21 10:30:57 +00:00
Hui Liu 8ba3e34f18 soc/mediatek/mt8188: Add VMCH, VMC support for MT8188
For MT8188, we need to enable and adjust VMCH and VMC to support SD
cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs.

TEST=measure 3.0V in VMCH and VMC.
BUG=b:236331724

Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 10:30:02 +00:00
Bo-Chen Chen 9d11cd7081 mb/google/geralt: Initialize PMICs in romstage
TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71cc69c74dd618f441140790af351095ead3f6f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65759
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 10:29:31 +00:00
Hui Liu f1d9e42269 soc/mediatek/mt8188: Add PMIF and PMIC init support
Add PMIF, SPI, SPMI and PMIC init code.

These PMIC settings are used by MediaTek internally. We can find these
registers in "MT6365_PMIC_Data_Sheet_V1.4.pdf" and
"MT6315 datasheet v1.3.pdf". The setting values are provided by MeidaTek
designers.

TEST=build pass
BUG=b:233720142

Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I05a51894b130a59c28d957b64d6401c8bb9cee91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-21 10:28:24 +00:00
Rex-BC Chen 823dcea39c soc/mediatek: Create a function to check ulposc
We will use the same drivers for checking ulposc in MT8188, so we add a
new function pmif_ulposc_check() to common.

TEST=build pass
BUG=b:233720142

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-21 10:27:27 +00:00
Yu-Ping Wu b9c1ce67a5 mg/google/corsola: Enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED
Ti50 hasn't implemented version reading yet. To avoid the confusing
error message

 Did not recognize Cr50 version format

enable TI50_FIRMWARE_VERSION_NOT_SUPPORTED to make clear that this
feature is not supported.

BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I18dd4b5bc05c2af06627275968e49aba048ba05e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-07-21 10:26:47 +00:00
Subrata Banik 06e11f4b09 mb/google/rex: Pulling GPIO programming early to get debug msg
This patch moves the early GPIO programming from
`bootblock_mainboard_init` to `bootblock_mainboard_early_init`.

It will help to get the early debug prints as below.

TEST=Without this CL the initial report platform information
was missing as below:

[DEBUG]  VBOOT: Loading verstage.
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
         of 0x2000 bytes
[INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0 in
         mcache @0xfef84d50

With this CL the complete bootblock serial msg is coming.
[NOTE ]  coreboot-.mtl.po.ww29.5 Fri Jul 15 21:47:36 UTC 2022
         bootblock starting (log level: 8)...
[DEBUG]  CPU: Genuine Intel(R) 0000 @
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: f0270108
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d14 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG]  IGD: device id 7d55 (rev 00) is MeteorLake-P GT2
[DEBUG]  VBOOT: Loading verstage.
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1c04000.
[DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area COREBOOT found @ 1c09000 (4157440 bytes)
[INFO ]  CBFS: mcache @0xfef84a00 built for 18 files, used 0x414
         of 0x2000 bytes
[INFO ]  CBFS: Found 'fallback/verstage' @0x24d240 size 0x133d0
         in mcache @0xfef84d50

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e092cd749359e54fe518de21671275af4b03062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65986
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-07-21 07:15:54 +00:00
Robert Zieba 5725a9b82b mainboard/google/guybrush: Update Wake-On-LAN functionality
The generic wifi driver currently contains a lot of intel specific
functionality that results in it not working properly on AMD platforms.
This commit updates the base device tree to use the generic PCIe driver
instead.

BUG=none
TEST=Ran on nipperkin device, dumped SSDT and checked wakeup sources

Change-Id: Iafbc68c1ae33ccc260889f0b39fc5fe8a59d7aca
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65990
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:33:12 +00:00
Robert Zieba 247d034a7a mainboard/google/skyrim/baseboard: Enable Wake-On-LAN functionality
The generic wifi driver currently contains a lot of intel-specific
functionality that interferes with enabling wake-on-lan. This commit
changes the device tree to use the generic PCIe driver which better
supports this functionality.

BUG=b:237682766
TEST=Booted on skyrim device and verified that wake on LAN works

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I5d15d33fd0a152eb3bf2bfe78e802483a701e750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65800
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:32:43 +00:00
Robert Zieba d1cc04b5eb drivers/pci/generic: Add support for `_PRW`
This commit adds support for `_PRW` in this driver.

BUG=b:237682766
TEST=Built and booted on Skyrim device, dumped SSDT

Change-Id: Ife4ba48994cbf993bc88df8354576336438e4258
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65799
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:31:22 +00:00
Robert Zieba 23e94a4e23 drivers/pcie/generic: Add support for custom ACPI name
This commit adds code to allow the driver to use an ACPI device name
that is set in the device tree.

BUG=b:237682766
TEST=Boot changes on Skyrim device, dumped SSDT

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ie40a335e35b8ac83658e67d7cfba0750dd4784ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65798
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:24:51 +00:00
Robert Zieba 5609f7a684 drivers/pcie/generic: Clean up driver
This removes unneeded and unused functionality in the driver as part of
an effort to make the driver more generic and useful. The things that
have been removed are: `DmaProperty` and its associated `is_untrusted`
config, `_DSD` generation, and the companion device functionality. This
driver isn't currently used anywhere so there won't be any issues from
removing the above functionality.

BUG=b:237682766
TEST=Built and booted coreboot on Skyrim device

Change-Id: I0abd9148ab66ea9426069102ecc8c2fa77fea98e
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:23:40 +00:00
Fred Reitberger 65f558f576 soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write
The SPI_RESTRICTED_CMD register is not a PCI configuration register.  It
is memory mapped from the SPI bar.

Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50

TEST=Compile tested only

Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63305
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-20 22:22:14 +00:00
Tony Huang 6a0e470197 mb/google/brya/var/agah: Adjust I2C speed
Adjust I2C speed for codec, TPM, touchpad.

BUG=b:237691531
TEST=Built and verified adjusted I2C speed < 400KHz

Change-Id: I203d137d61019235ddf38ef74607427db2a7e975
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-20 20:29:57 +00:00
Lijian Zhao 6f4c18db0d Documentation: Fix broken link
Link to Linux kernel coding style changed, fix it.

Change-Id: I9792d360d301b93c255306488c90375c6cc882c4
Signed-off-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-07-20 20:29:40 +00:00
Arthur Heymans 28de28d8de arch/x86/*.ld: Don't use CPP to include linker scripts
This makes inspection of linker scripts in the build dir a little
easier.

Change-Id: I509faa4cee2c9f066f4e20f6038349e1165a619a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-20 20:29:13 +00:00
Arthur Heymans 3e914d3726 arch/arm64,arm: Prepare for !SEPARATE_ROMSTAGE
Prepare platforms for linking romstage code in the bootblock.

Change-Id: Ic20799b4d6e3f62cd05791a2bd275000a12cc83c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-20 20:28:39 +00:00