Commit Graph

13130 Commits

Author SHA1 Message Date
Patrick Georgi 387cd3cf2f build system: make CONFIG_* symbols disappear from objects
We don't actually want to see them in the binaries.

Change-Id: I37b53ef7dcbe05d81a8322d528c9aae102115134
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9180
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01 00:29:18 +02:00
Aaron Durbin 67514a7a5f cbfs: remove cbfs_core.h includes
Some of the files which include cbfs_core.h don't even need
the header definition while others just need the cbfs API
which can be obtained from cbfs.h.

Change-Id: I34f3b7c67f64380dcf957e662ffca2baefc31a90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9126
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31 23:03:10 +02:00
Aaron Durbin f786652af1 cbfs: add cbfs_serialized.h header file
The serialized format of CBFS is separate from the APIs
used to traverse and read from CBFS. Separate those out
so they can be consumed as a standalone header.

Change-Id: I09f71d9c474ee9f23a62b0062ffa777963d1a4dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9125
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-31 23:01:39 +02:00
Duncan Laurie bf5407cd49 chromeec: Clear post code before reboot to RO
When doing an EC requested reboot to RO mode clear the
saved post code in order to prevent confusing events in
the log where the system is rebooted intentionally.

BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus, run FAFT, check for odd
eventlog entries about last post code 0x31 when it is
rebooted during samus romstage entry point.

Original-Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e32d7a7e54e7006b84509dbc2bfe9b4b022eba71)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iad816669fb4054260f995f6f0bfb140121aaddff
Reviewed-on: http://review.coreboot.org/9176
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-31 20:21:43 +02:00
Aaron Durbin 6e76fff969 program loading: provide one cache maintenance callback
Instead of having 2 different functions to call when a program
is loaded provide a single callback with flags parameter. The
previous callbacks for cache management routines did this:

for_each_program_segment:
	arch_program_segment_loaded(start, size);
arch_program_loaded();

Now, use one callback instead:
for_each_program_segment:
	arch_segment_loaded(start, size, SEG_FINAL?);

Change-Id: I3811cba92e3355d172f605e4444f053321b07a2a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31 19:42:08 +02:00
Aaron Durbin ebf2ed4621 payload loading: remove passing of struct payload
There's no need to keep track of struct payload within
the boot state machine. It is completely contained within
the payload loader module.

Change-Id: I16fcecf43d7fb41fc311955fdb82eabbd5c96b11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8836
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31 19:31:57 +02:00
Aaron Durbin fcfdff84f4 loading: move ramstage cache function declarations
The functions related to caching ramstage were in cbfs.h.
Now that the loading code is separate move those declarations
to the common program_loading.h.

Change-Id: Ib22ef8a9c66e1d2b53388bceb8386baa6302d28b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-31 19:30:07 +02:00
Aaron Durbin 7c2eb0d78b mips: don't open code romstage loading
Use the run_romstage() API to prevent code duplication
and more maintenance for any API changes or features.

Change-Id: I4122b813cccf4dc0703f256e1245deeeb90deeb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9172
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-31 07:55:25 +02:00
Aaron Durbin 5b9384c3fc cbfs: remove run_address()
The run_address() function is not used. Remove it.

Change-Id: I96de4cf0a529b08943ff8281cedead642eb415de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9124
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-31 06:58:22 +02:00
Aaron Durbin 98d9678b74 google/veyron_pinky: Don't auto select CHROMEOS
Indicate to reset of coreboot that MAINBOARD_HAS_CHROMEOS
instead of auto-selecting it.

Change-Id: Ide84bc0d8f801c79457dc05f768dd717a8a2f700
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9154
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 23:38:56 +02:00
Aaron Durbin e73dae4bf5 x86: fix SMM programs linked with gc-sections
Commit f69a99db (coreboot: x86: enable gc-sections) added
gc-sections to the linker command line. The SMM-specific
linker scripts were not interrogated to see if all the
sections were being included properly. .data, .bss, and .sbss
did not have the proper globs set to put the SMM programs in
the expected order.

Lastly, explicitly set the ENTRY for the SMM programs.

Change-Id: Ibb579d18d4819af666d6ec7dfc30776e8c404b71
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9160
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-30 23:03:27 +02:00
Aaron Durbin 83a8df52b0 broadwell: fix HAVE_REFCODE_BLOB build errors
When building HAVE_REFCODE_BLOB there are a couple of errors. One
is a failure building !CHROME_OS. The other is from a header
change where console_tx_byte() was declared.

Change-Id: I4110debd6d3818d4a803ed22037166c226f2ed11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9142
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30 22:06:27 +02:00
Aaron Durbin 43b7db7df0 baytrail: fix HAVE_REFCODE_BLOB build errors
When building HAVE_REFCODE_BLOB there are a couple of errors. One
is a failure building !CHROME_OS. The other is from a header
change where console_tx_byte() was declared.

Change-Id: Ia912902e8276d13b8e1716aa16c57b111579a03d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9141
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-03-30 22:06:09 +02:00
Aaron Durbin 42bab14a12 google/nyan_blaze: Don't auto select CHROMEOS
Indicate to rest of coreboot that MAINBOARD_HAS_CHROMEOS
instead of auto-selecting it.

Change-Id: I61cde263f4ad7bd6758a61fc54c456c2ad2f343e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9153
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-30 21:59:01 +02:00
Martin Roth 72a8e5e751 Update hex values to CBFS binary name types in Makefiles
These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names.  The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.

This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.

Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 21:47:15 +02:00
Martin Roth dde307c01a cbfstool: add filetypes for FSP, MRC, SPC and MRC_CACHE
This adds a few new file types to cbfstool.  Currently these
files are being added using bare hex values in the coreboot
makefiles.  This patch is just to make the values official and
to help get rid of some confusion in the values used within the
makefiles.

All of these new types are roughly equivalent to raw.

Change-Id: I37c4180a247136cd98080f6f7609d3cf905a62f5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 21:45:11 +02:00
Patrick Georgi e0935bb405 build system: mips is a valid nickname for mipsel
Change-Id: I5829a96cbb0af0398113efbdf34dfa3d102bf4c8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9146
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-03-30 21:42:40 +02:00
Vadim Bendebury 9b0584677f Avoid 64bit math on MIPS platforms
Low level 64 bit division and modulo functions are not available for
MIPS platforms, but are required by the printk formatter.

Modify the code to avoid 64 bit math when building for MIPS. In case
the user does print a value exceeding 2^32, send a few junk characters
to the output to indicate a corrupted value printed.

[pg: add the printed sequence to the comment, so git grep can find it]

BRANCH=none
BUG=none
TEST=startup code on Urara properly prints CBFS address values which
     are passed as 64 bit integers.

Change-Id: Ie777019cd8d55c53d5e816fbacfe79893c3d64c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8347f914a9cceca017668f8387ba679c2c79e66d
Original-Change-Id: I25b8a900b3ba4ec1da3446dcc5f03101d5cdb757
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232294
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9162
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 21:42:38 +02:00
Patrick Georgi 3bc2999cb0 mips: bring payload execution to current standards
Change-Id: Id7f438a95fc7c7b41ce3d0fb419b0b455f8367a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9167
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:24 +02:00
Patrick Georgi 6f723c2692 mips: fix write_table
This replicates commit 3f7ad7b216 and
commit 823edda98e for mips.

Change-Id: Id97e1fefa20cfa3bcb2cf0336b5a4ff7d9fe813b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9166
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:23 +02:00
Patrick Georgi 146d05da93 imgtec/pistachio: Bring uart driver to modern standards
The console interface changed in upstream, and the
driver didn't reflect that yet.
This wasn't obvious because the driver wasn't compiled
at all.

Change-Id: Id18391e62e7ebd8f5fc929838ce27bf414e364f9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9165
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:22 +02:00
Patrick Georgi 4697d09f1a emulation/imgvp-pistachio: Drop board
This doesn't even compile in downstream.

Change-Id: Ic7b3736db86e8de155e0f37afa970ce5095396fa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9164
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:21 +02:00
Patrick Georgi 6b65f0d8bd mips: Simplify architecture specific Makefile.inc
The mips Makefile was inherited from x86 and so included lots
of stuff that is necessary on x86 but nowhere else.
That cruft is now gone.

It also adopts the non-x86 approach of handling linker scripts,
hardcoding an include to ldoptions there, instead of manual
concatenation (of just one file plus options).

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ibf0c7096f9425572d8f83837aa6a253fd91e212c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-30 20:41:20 +02:00
Patrick Georgi 10f86b0bd8 build system: generalize src-to-obj
It can now be used on any list of files instead of assuming
to work on $($(class)-src).

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ib77afedd4c3f847963497beea503f5447a7c6e28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9161
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-30 20:41:17 +02:00
Patrick Georgi cbe27469c1 x86/smm: Move SMM configuration out of generic Makefile
It's x86 specific.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Iacb91b47c89041435dd27c2c9ad34a231adf21d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9115
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:15 +02:00
Patrick Georgi 2459aeea0b build system: provide generic compiler flag variables
Introduce generic-$(type)-ccopts and $(class)-generic-ccopts
to declare compiler flags that apply to all files of a certain
type or of a certain class. Then use them.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I655688e82a0cc5bad89b6f55dc217b9f66b64604
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:13 +02:00
Patrick Georgi 08f2ab6aac build system: rename mips/bootblock.inc to mips/bootblock.S
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I192fa50989b586fd8e967d4c22db56ac9de7a30e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9108
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 20:41:11 +02:00
Patrick Georgi 5602f2cd73 crossgcc: Fix calling outside util/crossgcc
Copy $0 contains the path, and we cd into that early.

Change-Id: If4124d16dea97b5eee4996bdfa3eae3d5d94c5d1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/9145
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 12:04:39 +02:00
Idwer Vollering b5589026c7 util/genbuild_h: work around GNU date
Confirmed to work on FreeBSD using sh from base and bash from ports.
Verified to not break M.O. on Linux.

Change-Id: I3bce724c889c7fb760b30b25e9fc0b74620e2c53
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/9056
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-29 22:45:08 +02:00
Patrick Georgi 00d48464b9 build system: remove intermediate link step in vboot
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I5405c0ee6bee203281e723feaecaee57fad8f6cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 22:41:26 +02:00
Patrick Georgi 8688defd50 mips: mips, not mipsel
Change-Id: I49df089d3fd5f578702dcc32be08bf6245277a45
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9149
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-03-29 22:38:57 +02:00
Patrick Georgi 99f1a61a42 mips: add verstage configuration
Change-Id: I79b4969c34500fd51b1ce2ad751bc0723ee0afa2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9147
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 22:38:53 +02:00
Patrick Georgi 0d06b2dee9 crossgcc: Build mipsel-elf, not mips-elf
The build system expects mipsel, and it's the more
precise name, too.

Change-Id: I9e1135385b3f1374b3179ecf5e11a1d60bc17ef7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/9144
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-29 22:37:22 +02:00
Timothy Pearson 4785f2a358 arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make public
Change-Id: Ib85701965337bb6231d8df59d43789dfe8a036d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9136
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-29 16:34:07 +02:00
Timothy Pearson 821217b60f arch/x86/boot/smbios: Add additional SMBIOS defines and enums
Change-Id: I337584d1f4ce32094c24478a99418e0775cf9ab5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9135
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-29 16:33:00 +02:00
Timothy Pearson fef509499f mainboard/asus/kfsn4-dre: Enable BIOS recovery jumper
The ASUS KFSN4-DRE has a physical BIOS recovery jumper;
force coreboot into fallback mode if that jumper is set.

Change-Id: I513299c3e3261fc76133a49813685d48c53a172a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9156
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-29 08:44:34 +02:00
Timothy Pearson a080260dbd drivers/pc80/mc146818rtc_early: Honor Kconfig reboot count clear setting
Change-Id: I6426ea2ca1732a6edfae059fe5dbf4f398bc9b98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9155
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-29 00:42:34 +01:00
Patrick Georgi 68bfe16b44 armv8/secmon: SECMON_SRC is really SECMON_BIN
It points to a binary.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I164d7f717a9523d187e2c215083e176b59fd5acc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9113
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:15:57 +01:00
Patrick Georgi 70a6b4f931 arch/x86: Guard option table specific rules with HAVE_OPTION_TABLE
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: Ia22c9fcbf8c629d0eb3f1356f80c4565f117d8b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9110
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:15:54 +01:00
Patrick Georgi ea9f308018 build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28 19:14:47 +01:00
Patrick Georgi 276ff99a07 arch/arm64: Drop extra comment
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I362e2f6a978de23e72e6fc9c83bc99457cd76d9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:14:37 +01:00
Patrick Georgi 58fef67436 arch/arm: drop extra comment
This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I8a5dc66d8c0dc4ccdb6dc3d66b8cdbf50dc976ca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9111
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 19:14:34 +01:00
Aaron Durbin 8880df10fa pistachio: don't open code ramstage loading
Use the run_ramstage() function to load and run ramstage.

Change-Id: I783801bf506fa2f9608eefe1cd20257292c80af5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-28 17:43:47 +01:00
Aaron Durbin 910a00dc30 mips: fix API expectations that break builds
Add the approrpiate car* empty implementations as well as types
included within the rest of coreboot to start building correctly.

Change-Id: Ifaf10281f9a9e28f518f4694630cbffa3f8d187d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9150
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
2015-03-28 16:44:24 +01:00
Vadim Bendebury b7cf11573d storm: need larger CBFS cache
With VPD blob of certain format, CBFS cache on storm proves to be not
large enough. This patch makes it bigger, it is still well above the
area preserved for the NSS.

BUG=chrome-os-partner:32152
TEST=the system now boots with the VPD it used to fail booting.

Change-Id: Iee1214b218ee3f8aca28797841501c227549affb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f19ca8cb9a2efa1d295f038730ed06ec9ceb8c4
Original-Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219572
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:36 +01:00
Vadim Bendebury f32ef133dd storm: fix SW_RESET signal polarity
The actual level required to take the ethernet switch out of reset is
low, not high.

BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
     switch's LED blink once, as was the case with proto0.

Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353
Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217416
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9121
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:34 +01:00
Vadim Bendebury c7bbc04544 storm: deassert SW_RESET signal at startup
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.

BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
     switch's LED blink once, as was the case with proto0.

Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154
Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217087
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9120
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:20 +01:00
Vadim Bendebury 2786ce0b48 storm: make sure board ID is calculated only once
Figuring out board_id on storm requires reading tertiary gpios, which
takes time. Let's calculate it once and reuse it when necessary.

BUG=none
TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2
     respectively.

Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1
Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217086
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9119
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:17 +01:00
Vadim Bendebury 1de971dd32 storm: reset TPM properly on proto0
The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22
pin instead of the system reset. This causes all kind of TPM behavior
problems and requires frequent power cycles. Adding explicit TPM reset
makes all those problems go away.

BUG=chrome-os-partner:30705, chrome-os-partner:30829
TEST=tried resetting proto0 at different moments during boot up - the
     TPM does not fail anymore.

Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6
Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211497
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9118
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:11 +01:00
Vadim Bendebury c6d30405f2 storm: supply vboot GPIO settings in coreboot table
Storm provides three real and two fake gpios. To keep things simple,
define them all as active low and provide appropriate values for the
fake ones.

BUG=chrome-os-partner:30705
TEST=with the appropriate depthcharge change booted proto0, observed
     appropriate behavior following the dev switch setting

Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d
Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210922
Reviewed-on: http://review.coreboot.org/9117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28 08:48:08 +01:00