Commit Graph

18571 Commits

Author SHA1 Message Date
Aaron Durbin bcbb205454 build system: add easier targetting of cbfstool options per region
The first attempt of providing a options-for-region function to call
to determining a file's cbfstool options would work, but it means there
can only be one instance which has to handle all of the files that may
need an override. That logic can be problematic in impelementation.

Instead, provide a mechanism to target cbfstool options for a given
CBFS region where the implementation is tightly coupled in the build
system to where the file as requested to be added to cbfs. This allows
there to be a base set of cbfstool options while more easily extending
arguments on specific regions.

Example which adds '-b 0x10000' only for the COREBOOT CBFS region:
cbfs-files-y += file.bin
file.bin-COREBOOT-cbfstool-opts := -b 0x10000

Change-Id: Idfafb0205be42768adb04bb0a30fe46a9ca1bd57
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14640
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-05 07:59:54 +02:00
Werner Zeh 6c481755c4 drivers/spi: Add support for Micron N25Q128A
Although we have already support for the flash chip N25Q128 there is a
similar type available which has the same geometry and opcodes but
unfortunately a slightly different device type ID. While the already
supported N25Q128 has the ID 0xbb18 this one has the ID 0xba18.

To make both types available in the flash support table, use N25Q128A as
the flash name. This name can be found in the datasheet which can be
found here:
https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_128mb_3v_65nm.pdf

TEST=Booted and verified that MRC cache could be written

Change-Id: I02a47692efb23a9a06a289c367488abd256b8e0c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16061
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05 07:41:59 +02:00
Lee Leahy f61de073e5 drivers/intel/fsp2_0: Add checklist support
Add the Kconfig value to point to the checklist data files.

TEST=Build and run on Galileo Gen2

Change-Id: I3737b46162214fad139382193de944ec5d175645
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16039
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 06:34:39 +02:00
Lee Leahy 3de7d4a9b2 soc/intel/quark: Add bootblock_c_entry
Add the bootblock_c_entry routine to make it more explicit where the
code transitions from assembler to C.

TEST=Build and run on Galileo Gen2

Change-Id: Ib5f580c30b58d3c82fedddf63c368e617d401515
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:55:41 +02:00
Lee Leahy f74ce24de1 soc/intel/quark: Clean up debug output levels
Change the debug output levels for quark:
*  Remove excess debug output
*  Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c

TEST=Build and run on Galileo Gen2

Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05 01:55:17 +02:00
Lee Leahy d52636113a soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW).  Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.

TEST=Build and run on Galileo Gen2.

Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05 01:54:55 +02:00
Lee Leahy f26fc0f28b soc/intel/quark: Add FSP 2.0 romstage support
Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:53:49 +02:00
Lee Leahy 102f625360 soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.

TEST=Build and run bootblock on Galileo Gen2

Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:50:45 +02:00
Julius Werner 6e05c33626 checkpatch: Add BLOCK_COMMENT_STYLE to ignore list
Linux' newest checkpatch.pl flags comments like these:

/* This is a concise 2-line comment that explains what the code does in
 * sufficient detail without wasting too much vertical space. */
do_stuff_that_needs_explaining();

Comments like these have been used in our code base for a long time and
I don't think we should disallow them now. Ending the comment on the
same line doesn't really hurt readability and wastes less screen real
estate (which in turn usually helps overall code comprehension).

Change-Id: Ifd57f3d3a62738165024cb4b2e75a4f815a57922
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16060
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-05 00:01:55 +02:00
Patrick Georgi 88a25ec20a 3rdparty/vboot: update to latest master
Half a year has passed. Fixes went in. Probably bugs, too.
However, nobody really supports our local vboot version anymore.

Change-Id: I5042f23686dfe98e540c482f744e9df2d7df3b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16055
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
2016-08-04 23:22:36 +02:00
Martin Roth 9a162d7791 toolchain.inc: Update 'required toolchain' error text
The old text said:
*** building <STAGE> without the required toolchain.  Stop.

Where <STAGE> could be any of the coreboot stages - bootblock, verstage,
ramstage, romstage.

This error message was very misleading though, because what it actually
meant was that it didn't know what architecture was required to build
the stage, not that the toolchain was missing.
Update the text to better reflect the actual issue, and to give the
user a hint as to what to look for:
*** The toolchain architecture for <STAGE> is unknown.
*** Check your .config file for CONFIG_ARCH_<STAGE>_* settings.  Stop.

Change-Id: Ic2a4f60c1f25e0f5e1ebde76781bcb8da0987d82
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16024
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
2016-08-04 21:48:27 +02:00
Timothy Pearson 751bff14db sb/amd/sb700: Do not reset fifo after skipping the sent bytes
Port commit e08493 to the SB700 platform

Change-Id: Ie18c6cc0ccb31a0d16a80fcb4c2e147c19e228fe
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/16054
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04 21:47:50 +02:00
Paul Kocialkowski 8ff24803a3 chromeec: Chrome EC firmware source selection for EC and PD firmwares
In some cases, we don't want the Chrome EC firmwares (both EC and PD)
built directly by the coreboot build system or included in images at
all. This is already supported with EC_EXTERNAL_FIRMWARE but it does
implement a binary (build and include) or (neither build nor include)
policy.

Some cases require the ability to separately control whether the EC
and PD firmwares should be built and included by the coreboot build
system, only included from externally-built images or not included
at all.

This introduces config changes implementing that behaviour, renaming
options to make it clear that they are specific to the Chrome EC.

Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/16033
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04 17:18:38 +02:00
Jonathan Neuschäfer 5690f0e6d8 src/arch/riscv/id.S: Don't hardcode the strings
Change-Id: Ide87c45806c5e58775c77e7f780efb4cf81a70c9
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16014
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-04 17:17:38 +02:00
Shaunak Saha 60b4618a84 soc/apollolake: Return correct wake status in _SWS
Wake status is calculated from the four pairs of gpe0 in
cbmem CBMEM_ID_POWER_STATE which is filled very early
in romstage and depends on the routing information in
PMC GPE_CFG register. Coreboot sets the proper value
of routing based on devicetree from pmc_init. But when
system goes to S3 on waking up PMC is writing default
values again in GPE_CFG which results in returning
wrong wake status in _SWS. This patch corrects that
behaviour by correcting the gpe0 pairs in cbmem after
PMC sets the routing table in resume path.

BUG=chrome-os-partner:54876
TEST=On resume through powerbtn, lidopen, keyboard press,  etc.
     we are getting proper wake status.

Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16040
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-04 16:14:14 +02:00
Jagadish Krishnamoorthy b6739d1b56 soc/intel/apollolake: Configure gpio ownership
For the gpio based irq to work, the ownership of the pad
should be changed to GPIO_DRIVER.
Provide an option in the gpio defs to configure the PAD onwership.

BUG=chrome-os-partner:54371
TEST=none

Change-Id: I26d242d25d2034049340adf526045308fcdebbc0
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-04 16:13:34 +02:00
Shankar, Vaibhav fec95be8b6 google/reef: Add GPIO changes to assert SLP_S0/Reset signal
PMIC/PMU: Set the iosstates for PMIC to assert the reset
signal, PMU to assert SLP_S0 signal.

Change-Id: If5a6a1cb8f065a8c3a6a19d9441a21d60b39e579
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16031
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-04 16:12:54 +02:00
Barnali Sarkar d03596f4ca soc/intel/skylake: Correct address of I2C5 Device
This corrects the address of the I2C5 Device. The I2C
Controller #5 is on PCI Bus 0: Device 25: Function 1. The ACPI
Address Encoding Logic is - High word = Device #.
                            Low word = Function #.
So, I2C5 (_ADR) = 0x0019 0001.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu

Change-Id: I4719a843260ef58cc2307e909e9ccbffea519177
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04 16:12:13 +02:00
Furquan Shaikh e85de02fd4 lib/timestamp: Add timestamps to CBMEM in POSTCAR stage
POSTCAR stage has cbmem online. So, all timestamps need to be added to
cbmem timestamp region.

BUG=chrome-os-partner:55848
TEST=Verified that timestamps added in postcar show up in cbmem -t.

Change-Id: I64af8c1e67b107d9adb09de57c20ea728981f07c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16032
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04 03:27:08 +02:00
Patrick Georgi b9eee8e468 lenovo/x60: Fetch 16 bits when trying to parse bit 13
I'm not sure if that's the right fix here, but assuming the bit mask is
right, the inb is wrong.

Change-Id: I7e33019af088780a09be12513200bec63734bf97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1229556
Reviewed-on: https://review.coreboot.org/16026
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03 22:53:21 +02:00
Timothy Pearson d6319e8cc0 sb/amd/sb[6|7|8]00: Initialize PIC
The PIC was not initialized, leading to hangs when booting
Linux as a payload.  This error was hidden by both SeaBIOS
and GRUB due to both payloads initializing the PIC as a
matter of routine.

Change-Id: I9a3b9bd831d4dafdd0bb82ea023026a10fe7efca
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/16018
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-03 22:08:01 +02:00
Vadim Bendebury 9e561f8e80 spi/tpm: read TPM version in larger chunks
The TPM version string has become much longer recently, and the
TPM_FW_VER register available on VID 1ae0 devices supports reading in
arbitrary size quantities.

Let's read 50 bytes at a time to reduce the SPI register read wrapper
overhead, and increase the length limit to 300 bytes to accommodate
longer version strings.

TEST=verified on the Kevin device:
 localhost ~ # grep cr50 /sys/firmware/log
 Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c
 cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha

Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/16000
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 20:07:40 +02:00
Kan Yan d1a00515ff google/gale: Add more board ID variants
EVT1 has two board IDs.
Use binary first mode of base3 encoding for board ID.

BUG=chrome-os-partner:55320
TEST=None.
BRANCH=None

Change-Id: I1cac1f74207f42616111d39db5c0494b7d1a0fb2
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 2b16cc74c4c147315b7db345678bbaf536ab4a7b
Original-Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364623
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-on: https://review.coreboot.org/16030
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-08-03 18:23:47 +02:00
Julius Werner 40d62f3db7 google/gru: Add code to support I2C TPM for Kevin
Coming Kevin revisions will switch back to an I2C TPM. This patch adds
the required configuration options and code to support that. Since the
TPM type can currently only be changed at compile time, we can no longer
support older Kevins with the same image. In order to build for Kevin
revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2.

BRANCH=None
BUG=chrome-os-partner:55523
TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage
binary had the appropriate code differences.

Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9
Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/364222
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16029
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-08-03 18:23:23 +02:00
Julius Werner 5e6771b1cb google/gru: Add support for Gru rev1
This patch adds support for the Gru rev1 board. This board differs from
rev0 by no longer relying on the I2C backlight booster and requiring the
same ODT SDRAM settings as newer Kevin boards.

BRANCH=None
BUG=chrome-os-partner:55087
TEST=None

Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28
Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/364624
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16028
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03 18:23:08 +02:00
Martin Roth 47ca65a791 payloads/coreinfo: Set KCONFIG_CONFIG value
The KCONFIG_CONFIG value was previously keeping the value set by
coreboot's makefile. That caused it to overwrite coreboot's .config,
making the current coreinfo build and the next coreboot build fail
with the curious error that you were building without the correct
toolchain.

Change-Id: I973b0c36e7227135a5c2d6d261e08889857aaaf1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16023
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 18:12:06 +02:00
Lee Leahy 5fafc6ad54 soc/intel/quark: Support access to CPU CR registers
Add support to access CR0 and CR4.

TEST=Build and run on Galileo Gen2.

Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:03:46 +02:00
Lee Leahy 72fe7acbbb util/checklist: Place tables in proper boot order
during the boot, romstage occurs before postchar which is before
ramstage.  Place the tables in the proper boot order when generating
the final webpage.

TEST=Build and run on Galileo Gen2

Change-Id: I5df3ceb797aced58fe5ea3d10d78254a27341e47
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:01:32 +02:00
Lee Leahy 3440db5827 util/checklist: Concatinate optional list to complete list
Don't require that the routines in the .optional file be listed in the
.complete data file.  Concatinate the two files when building the
complete symbol list.

TEST=Build and run on Galileo Gen2

Change-Id: I596134e1a19311d357aa0d93cfb33c7ca9801e2e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16037
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:00:57 +02:00
Lee Leahy 3741a0b225 util/checklist: Process .debug files before .elf files
Ensure that the output file is created by processing the .debug files
before the .elf files.

TEST=Build and run on Galileo Gen2

Change-Id: Ief8d774249c9d8eb313f3d10f04d7e4f2e3cf491
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:00:29 +02:00
Lee Leahy ce8ff85fe5 util/checklist: Add usage instructions
Document how to use the checklist and how to generate the data files.

TEST=Build and run on Amenia

Change-Id: Idffc0683e916cbc5a984028886dc3d89a01d0595
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:00:03 +02:00
Lee Leahy 77051e061f mainboard/intel/galileo: Add FSP 2.0 Kconfig support
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0
builds for Quark.

TEST=Build and run on Galileo Gen2

Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15864
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:49:20 +02:00
Lee Leahy 38e0cc0aa4 soc/intel/quark: Add header files for FSP 2.0
Add the FSP 2.0 header files for Quark.  These files were run through
the drivers/intel/fsp2_0/header_util to convert the data types so that
they are compatible with the coreboot build system.

TEST=Build and run on Galileo Gen2.

Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:48:53 +02:00
Lee Leahy 01728bb2ed soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.

TEST=Build and run on Galileo Gen2

Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 17:47:53 +02:00
Lee Leahy 3d0e3cf4b1 soc/intel/quark: Initialize MTRRs in bootblock
Initialize the MTRRs for use by bootblock and romstage.
Display the MTRRs.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib1d422c738820163f54771c65034ae77301237ec
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15861
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:46:36 +02:00
Lee Leahy 14d09264a2 soc/intel/quark: Remove use of EDK-II macros and data types
Include assert.h to use coreboot's ASSERT macro.
Replace the use of UINT32 data type with uint32_t.
Replace the use of UINT8 data type with uint8_t.

TEST=Build and run on Galileo Gen2

Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15858
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:31:39 +02:00
Werner Zeh 1cfb555e71 fsp_broadwell_de: Add DMAR table to ACPI
Create DMAR table for Broadwell-DE SoC.

TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and
     disassembled DMAR table using iasl. The table contents are as
     expected and the kernel loads DMAR table without errors.

Change-Id: I7933ba4f5f0539a50f2ab9a5571e502c84873ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15913
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-03 12:44:25 +02:00
Nico Huber 5407310e64 cbfstool: Check for excessive arguments
Change-Id: I66de6a33b43c284198c0a0a97c5c6a10f9b96e02
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16019
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 10:12:02 +02:00
Nico Huber 9ade717571 cbfstool: Check arguments to strtoul() where appropriate
The interface to strtoul() is a weird mess. It may or may not set errno
if no conversion is done. So check for empty strings and trailing
characters.

Change-Id: I82373d2a0102fc89144bd12376b5ea3b10c70153
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16012
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03 09:42:11 +02:00
Nico Huber f641a27b63 Makefile.inc: Strip output of `wc`
Apparently BSD's wc indents its output.

Change-Id: I77f50a4b7d6012782f1c1b42ba20a64721c186c8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16013
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 09:40:36 +02:00
Werner Zeh 21a5bff77b ACPI: Add code to create root port entry in DMAR table
PCI root ports with "Address Translation Service" capability can be
reported in DMAR table in the ATSR scope to let the OS know how to
handle these devices the right way when VT-d is used.
Add code to create an entry for a PCI root port using the type
"SCOPE_PCI_SUB".

Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15912
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 06:24:17 +02:00
Werner Zeh d4d76959c0 ACPI: Add code to include ATSR structure in DMAR table
DMAR tables can contain so called "Address Translation Service Reporting"
(ATSR) structure. It is applicable for platforms that support
Device-TLBs and describe PCI root ports that have this ability.
Add code to create this ATSR structure.

In addition, a function to fix up the size of the ATSR
structure is added as this is a new type and using the function
acpi_dmar_drhd_fixup() can lead to confusion.

Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15911
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 06:23:11 +02:00
Lee Leahy b0afbad8e1 mainboard/intel/galileo: Remove use of EDK-II macros & data types
Add assert.h to use coreboot's ASSERT macro.
Replace the use of UINT8 data type with uint8_t.

TEST=Build and run on Galileo Gen2.

Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15859
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03 06:22:33 +02:00
Lee Leahy d87d8eaca1 soc/intel/quark: Make ramstage relocatable
Relocate ramstage into CBMEM.

TEST=Build and run on Galileo Gen2

Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15994
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-03 06:21:22 +02:00
Lee Leahy b20d4ba57a drivers/intel/fsp2_0: Update the debug levels
Choose appropriate debug levels for the various messages in the FSP
driver.  Change:

* BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows
  builder to disable FSP driver output by selecting
  CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7

* BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the
  payload from successfully booting

TEST=Build and run on Galileo Gen2

Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16003
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:20:18 +02:00
Lee Leahy 94e502be7a drivers/intel/fsp2_0: Remove fsp_print_upd_info declaration
Remove unused function declaration.

TEST=Build and run on Galileo Gen2

Change-Id: Id971829c19c2535c975a68c44fb3697f60d0b4ad
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:19:42 +02:00
Lee Leahy 37b5ef26eb drivers/intel/fsp2_0: Disable display of FSP header
Add a Kconfig value to enable display of FSP header.  Move the display
code into a separate module to remove it entirely from the final image.

TEST=Build and run on Galileo Gen2

Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16002
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:19:03 +02:00
Lee Leahy 806fa2463f drivers/intel/fsp2_0: Handle FspNotify calls
Other SOC platforms need to handle the FspNotify calls in the same way
as Apollo Lake.  Migrate the FspNotify calls into the FSP 2.0 driver.
Provide a platform callback to handle anything else that needs to be
done after the FspNotify call.

Display the MTRRs before the first call to fsp_notify.

TEST=Build and run on Galileo Gen2

Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:17:31 +02:00
Lee Leahy 9671faa497 drivers/intel/fsp2_0: FSP driver handles all FSP errors
Move all FSP error handling into the FSP 2.0 driver.  This removes the
need to implement error handling within the SOC code.

TEST=Build and run on Galileo Gen2

Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:17:02 +02:00
Lee Leahy 52d0c682bf drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit
Verify that FSP is properly returning:
* HOB list pointer
* FSP_BOOTLOADER_TOLUM_HOB
* FSP_RESERVED_MEMORY_RESOURCE_HOB

TEST=Build and run on Galileo Gen2

Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15850
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:16:16 +02:00