Commit Graph

50192 Commits

Author SHA1 Message Date
Martin Roth 6202fbbe90 util/testing: Allow jenkins builders to skip testing areas
With the addition of the clang tests, the jenkins builds are taking a
really long time to run the tests.  This change allows the
"what-jenkins-does" build to be split into separate builds on jenkins.

Additionally, some jenkins builds like coverity don't need (or want)
to build clang or even the linters.

Update help with the variables.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0f8ac68c1bc8f8ff9be62d80db850355e742ee74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:06:20 +00:00
Martin Roth b5e9946227 util/testing: Add scanbuild test build to what-jenkins-does
This tests building a single target with scanbuild so to make sure that
option hasn't been broken.  Since it's a different type of build, it
hasn't previously been tested with what-jenkins-does.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8a74dac203f4d38c0cb30a0b64724e6f9095b9dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:06:05 +00:00
Martin Roth 676e0acb07 util/testing: Use new --name argument for abuild
This gets rid of the duplicated directory and xml filename and uses the
--name argument to abuild instead, which also updates the test name in
the junit xml file.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ibe538da42280696190b0a7a0c63fd86a63e40214
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:53 +00:00
Martin Roth 7df45bbc0c util/abuild: Add --name option to set name of abuild run
Previously, the testclass variable was only updated with the chromeos
or Kconfig option values, and the output directory and xml file names
were updated independently.

With the --name option, all of these can be set simultaneously. This
also prevents jenkins from seeing clang and gcc tests as the same
because the testclass variable wasn't updated.

If --name is not set, all behavior is as it was previously.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8f52779b92d213386a3eb371d1f30ee32ed48b85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69859
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:38 +00:00
Martin Roth 36dcabac05 util/testing: Call test-tools target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-tools target, make test-tools from what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id62d6bb1e729892ec123ea970ca8a31e03a812d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:24 +00:00
Martin Roth b399f103a1 util/testing: Update ABUILD_OPTIONS with long option names
It's hard to tell what is what with the short option names, so use the
long options here.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1371e098bba1077dedfaffa56287a28656197b40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69837
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:14 +00:00
Martin Roth dfafe798a6 util/testing: Call test-abuild target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-abuild target, make test-abuild from what-jenkins-does.

The test-abuild target had not been updated to use the ABUILD_OPTIONS
variable, so update it with the commands from what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4552193894c16301defb851eb3db4bdfbfa49803
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:05:03 +00:00
Martin Roth b3f60a53da util/testing: Call test-lint target from what-jenkins-does
Instead of having duplicate lines in the what-jenkins-does target and
the test-lint target, make test-lint with the --junit argument from
what-jenkins-does.

Now there's only one place to update when changing the call.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f90df76126f453fbcd91f4c4af5d784ac2dbe88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:04:53 +00:00
Martin Roth 2852cd2b22 util/testing: Unify cleanup in all targets
Instead of having the what-jenkins-does target clean up before building,
have it call the test_cleanup target.

Clean the tegra targets.

Remove distclean from test_cleanup target - I don't think that's
expected, and people might be upset by having their .config deleted.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia9d585df05343365c89e49b1c01dba9ba865003f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 20:04:25 +00:00
Karthikeyan Ramasubramanian 4763a5a470 soc/amd/mendocino: Increase CBFS_MCACHE size
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.

BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.

Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 19:56:34 +00:00
Elyes Haouas 9aea4ec9a5 cpu/intel/socket_*: Clean up Kconfig files
Remove SSE when SSE is already selected by supported CPUs.
Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig.

Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-21 18:42:17 +00:00
Martin Roth b04eda2ca1 util/abuild: check for PASSED_BOARDS before trying to show it
If no boards are tested by abuild, an error is currently shown because
no boards failed, but no boards passed either.  Account for this
possibility.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I097d3c728ca1acc652d5a1b7b49e57d01b0e513b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21 18:40:55 +00:00
Elyes Haouas 24ca80aab6 src/superio: Remove unnecessary space after casts
Change-Id: Iab76316f345fb0cf2ca2a3eaf40f64a1f1b7fc13
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69814
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-21 15:03:50 +00:00
Felix Held 1840f935d6 include/memlayout.h: update comment about VBOOT2 work buffer size
VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE is nowadays defined in
vboot/firmware/2lib/include/2constants.h, so update the comment.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7c9a5476ae06d4bac762da1729aff878b7d0965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-21 14:07:46 +00:00
Sridhar Siricilla e5ca71db06 soc/intel/common: Add support to read CPU and PCH Trace Hub modes
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.

For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.

TEST=Build code for Gimble

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-11-21 14:04:24 +00:00
Frank Chu 88019ddbdf mb/google/brya/var/marasov: update field STORAGE of fw_config
field STORAGE 30 31
	option STORAGE_UNKNOWN			0
	option STORAGE_NVME			1
	option STORAGE_UFS			2
end

BUG=b:254365935
TEST=emerge-brya coreboot.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I17f8a852808d279a1f2b08b364cd4e525a807560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69786
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-21 01:14:59 +00:00
Michał Żygowski e5b8a04f84 mainboard/msi/ms7d25: Configure NCT6687D pin for PECI
One register configuring multi-pin functions was outside of the Global
Configuration Registers space and skipped in the initial port patches.

Replicate the vendor configuration and set the Super I/O pin for PECI
functionality.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I90f142a1a9ee27dd061fc71b791bd4c7df97da6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68711
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 17:38:23 +00:00
Jonathan Zhang 1864f12fda device/pciexp: add pcie_find_dsn()
Add pcie_find_dsn() to detect and match PCIe device serial
number. In addition, vendor ID is matched when provided.

Change-Id: I54b6dc42c8da47cd7b4447ab23a6a21562c7618
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20 17:37:09 +00:00
Jonathan Zhang 3dcafa8774 acpi: Add initial support for CEDT
Add initial CEDT (CXL Early Discovery Table) support based on
CXL spec 2.0 section 9.14.1.

Add functions to create CEDT table (revision 1), and create CEDT
CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows
Structure (CFMWS).

TESTED=Create CEDT table on Intel Archer City CRB, dumped the
CEDT table and examined the content.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-20 17:35:04 +00:00
Martin Roth b7f92a0b6a util/kconfig: Add patch to move Kconfig deps to build/config
The change being reverted [1] caused all the Kconfig dependency files
to be generated at the top level of coreboot's build directory.

This reverts that behavior and puts the dependencies back where we're
used to them being.

[1] 1b9e740a81

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic4b48831705c3206e7c2e09f01d072d1cde9c9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69535
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 17:29:32 +00:00
Martin Roth bfdb489032 Docs: Add SPDX headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id229fb22d20c489db3dd7a59f29e7ac10174fd85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-20 15:24:32 +00:00
Jan Samek 97afddf36a drivers/i2c/rx6110sa/chip.h: Remove confusing bus speed comment
There is a note about the default I2C speed of this being 400 kHz
despite the logic in rx6110sa.c sets the fallback (correctly) to
100 kHz.

This information originally comes from the fact the dw_i2c bus
controller default speed is 400 kHz. This is irrelevant to
the default speed of this device as it can be used with any
bus controller.

BUG=none
TEST=coreboot builds correctly (no functional changes).

Change-Id: Ic0ffe5667574c59e1c1df952b84b8a3680b53341
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69545
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-20 02:05:53 +00:00
Sergii Dmytruk 97fe17ff59 security/tpm: make log format configurable via Kconfig
This commit doesn't add any new format options, just makes selecting
existing format explicit.

Ticket: https://ticket.coreboot.org/issues/422
Change-Id: I3903aff54e01093bc9ea75862bbf5989cc6e6c55
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-11-19 15:11:09 +00:00
zhaojohn 1d903a24dc mb/google/rex: Enable TCSS DisplayPort detection at preboot
This change enables the DisplayPort detection at preboot for Rex board.

BUG=b:247670186
TEST=Built image and validated DisplayPort feature at preboot on Rex.

Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 15:09:52 +00:00
zhaojohn 7e0b925162 soc/intel/common: Fix the TCSS DisplayPort detection flow
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.

BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.

Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 15:09:03 +00:00
Fred Reitberger 2b9ee5d79e vc/amd/fsp/glinda/platform_descriptors.h: Update for glinda
Update definitions on glinda used by birman.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I03065011581489b5345c16e225edc341e1d7811c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:47:48 +00:00
Fred Reitberger 4875a1f054 vc/amd/fsp/morgana/platform_descriptors.h: Update for morgana
Update definitions to match morgana FSP.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic893526789c05a298965702114d4a814466a5742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-19 02:46:49 +00:00
Caveh Jalali 4e71517e37 ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGER
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all
references.

BUG=b:216485035,b:258126464
BRANCH=none
TEST=none

Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-19 02:41:48 +00:00
Tyler Wang decd67efad mb/google/nissa/var/craask: Disable gpio export in crs for G2 touchscreen
BUG=b:235919755
Test=Check error message "Exposing GPIOs in Power Resource and _CRS"
not show in firmware log.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I21a47adde48555098d041b94d483cad308bdb717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-11-19 02:40:55 +00:00
Kapil Porwal 89ea31248e soc/intel/meteorlake: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from
 1) enabling ACPI Timer emulation in uCode.
 2) disabling the PM ACPI Timer.

Both actions are now done in coreboot.

`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.

Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").

NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.

BUG=none
TEST=Boot to OS on google/rex.

Excerpt from google/rex coreboot log:
[SPEW ]   EnableTcoTimer                      = 1

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-19 02:40:26 +00:00
Subrata Banik 20c64a1210 mb/google/rex: Disable `ACPI PM timer`
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that
ACPI PM timer remains disabled.

The PM timer (by PMC IP) consumes more power and blocks S0ix so the
timer is emulated by ucode to save power and unblock S0ix.

TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc
BIT 1 is set.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 19:48:14 +00:00
Martin Roth b699d61b99 mb/google/skyrim: Enable STB Spill-to-DRAM by default
BUG=b:231291430
TEST=See STB Spill-to-DRAM enabled

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib60b7fc2ba85c7a8025c9f8c6495e94049499f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69707
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18 18:01:19 +00:00
Julius Werner 4924cdb9ac build: List all Kconfigs in CBFS `config` file, compress it
The coreboot build system automatically adds a `config` file to CBFS
that lists the exact Kconfig configuration that this image was built
with. This is useful to reproduce a build after the fact or to check
whether support for a specific feature is enabled in the image.

However, the file is currently generated using the `savedefconfig`
command to Kconfig, which generates the minimal .config file that is
needed to produce the required config in a coreboot build. This is fine
for reproduction, but bad when you want to check if a certain config was
enabled, since many configs get enabled by default or pulled in through
another config's `select` statement and thus don't show up in the
defconfig.

This patch tries to fix that second use case by instead including the
full .config instead. In order to save some space, we can remove all
comments (e.g. `# CONFIG_XXX is not set`) from the file, which still
makes it easy to test for a specific config (if it's in the file you can
extract the right value, if not you can assume it was set to `n`). We
can also LZMA compress it since this file is never read by firmware
itself and only intended for later re-extraction via cbfstool, which
always has LZMA support included.

On a sample Trogdor device the existing (uncompressed) `config` file
takes up 519 bytes in CBFS, whereas the new (compressed) file after this
patch will take up 1832 bytes -- still a small amount that should
hopefully not break the bank for anyone.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-18 17:19:44 +00:00
Jan Samek be585d2ece drivers/i2c/rx6110sa/rx6110sa.c: Make log messages consistent
Set the logging message prefix to the device name instead of the
device path in order to make the output consistent with other
logging messages in this and other drivers.

Change-Id: Ib63b93d52aad220d17f1f4ee0d47a949933ec26d
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69718
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18 16:05:03 +00:00
Jan Samek 6f8fd5d397 mb/siemens/mc_ehl2/devicetree.cb: Use RV3028 bus_speed instead of dummy i2c device
Instead of creating a dummy I2C device in order to force Linux to
decrease the I2C bus speed, use the own 'bus_speed' field of RV3028
device config structure.

Linux should always set the bus speed to the speed of the slowest
device sitting on the bus. Hence the dummy device is not needed
here anymore.

BUG=none
TEST=See if the RV3028 RTC is visible and working (date/time can
be set/read) in Linux. At the time, a driver modification is needed
to add a match table for the "MCRY3028" ACPI HID. A proper kernel
patch is pending.

Change-Id: I6e269dc67d1fe2a6747fcf3bee224def7b553f08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69544
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-11-18 16:04:34 +00:00
Jan Samek 1560648197 drivers/i2c/rv3028c7: Add ACPI generation callbacks
Add ACPI generation callback to the driver after obtaining the
ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY").

Also add I2C bus speed field to the device config structure, which
is a required ACPI entry.

BUG=none
TEST=Disassemble the SSDT table and see whether the device entry
"MC28" is generated correctly. Also check whether the RV3028 driver
in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding
an ACPI match table to it containing the HID. A proper kernel patch
is pending.

Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-11-18 16:03:53 +00:00
Elyes Haouas b1bcd5bb8c lib/malloc.c: Fix log messages
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.

Change-Id: I6e4341555a3b03a531bd94ba5e36cbcadda9c663
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18 16:02:28 +00:00
Elyes Haouas 799c321914 cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18 16:00:45 +00:00
EricKY Cheng 9cbbba68b6 soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-18 15:54:49 +00:00
Johnson Wang 159e64ca25 soc/mediatek/mt8188: Enable and initialize EINT
Issue:
Device can't wake up using power key.

Root cause and solution:
EINT event mask register is used to mask EINT wakeup sources. All
wakeup sources are masked by default. So we add a driver here to unmask
all wakeup sources.

BUG=none
TEST=wake the device up by power key on MT8188 EVB.

Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-18 15:47:33 +00:00
Shelley Chen f6307ca9c2 soc/qualcomm/sc7280: Skip PCIe ops for eMMC SKUs
On Herobrine, we will determine if we have an NVMe device based on SKU
id.  Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.

BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
     on villager, which does not have NVMe and made sure that it boots
     still.  Check cbmem dump to make sure that device configuration
     entry is still low since it's not initializing PCIe devices:

     40:device configuration 730,203 (1,295)

Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-18 15:47:05 +00:00
Shelley Chen b5af064f54 mb/google/herobrine: Implement mainboard_needs_pcie_init
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links.  When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.

BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-11-18 15:46:22 +00:00
Sridhar Siricilla ce4dc66319 soc/intel/meteorlake: Add Meteor Lake MCH device ID
Add Meteor Lake MCH device ID 0x7d15.

TEST=Build and verify boot on MTL RVP

With patch, coreboot log:
`[DEBUG]  MCH: device id 7d15 (rev 00) is Meteorlake P`

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 15:45:56 +00:00
Krishna P Bhat D 1c6b02a8b6 mb/google/nissa: Modify FMD to redistribute buffer
Modify the chromeos FMD file for nissa variants to redistribute the
buffer in SI_ME region obtained due to CSE size optimizations to SI_BIOS
region.

1. Modify SI_ALL region size to 3712K. SI_DESC remains at 4K and SI_ME
is 3708K.
2. Modify SI_BIOS region to 12672K. This results in an addition of 32K
buffer each to FW_MAIN_A/B regions.

BUG=b:228936671
BRANCH=firmware-nissa-15217.B
TEST=Verify CSE FW update with new FMD and ME RW blobs on craask.

Cq-Depend: chrome-internal:5094491
Change-Id: I5ead2f81850a2aa79e677c7f271db672e235750a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18 03:39:35 +00:00
Johnny Li d7328abc95 mb/google/brya/variants/crota: Configure TDC current for VR domains.
+-----------+-------+-------+---------+-------------+----------+
| Setting   | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
|           |(mOhms)|(mOhms)|   (A)   |     (A)     |   (msec) |
+-----------+-------+-------+---------+-------------+----------+
|    IA     |  2.8  |  2.8  |    80   |      43     |  28000   |
+-----------+-------+-------+---------+-------------+----------+
|    GT     |  3.2  |  3.2  |    40   |      23     |  28000   |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.

BUG=b:256754175
TEST=Build test image and use PTAT to check IA and GT value
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: Ife36655f077bae567bff3c3e33f779c990cf5ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69135
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-11-18 00:38:25 +00:00
Arthur Heymans 457f77be37 Makefile.inc: Remove workaround ACPI warnings
No boards now have a missing dependency so remove the workaround.

Change-Id: I787f6aa588175ba620a068918c42edc9d257c3ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69514
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-18 00:14:13 +00:00
Martin Roth 35e09ec8ae util/kconfig: Move Kconfig deps back into build/config
revert commit 1b9e740a8 (kconfig: fix failing to generate auto.conf) [1]

The above change caused all of the enabled kconfig options to be written
into the top level build directory.  We don't want that, so go back to
the old behavior for the coreboot tree.

[1] 1b9e740a81

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2904f69a5d85337ad0a6b48590ccd4b4a6e38b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-17 23:37:48 +00:00
Kyösti Mälkki 2e65e9cb69 soc/amd: Use ioapic helper functions
Calling setup_ioapic() was only correct for the
IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs.

Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17 23:31:59 +00:00
Arthur Heymans 87d4f114a2 {ec/superio}/acpi: Remove _PRS if no _SRS is implemented
_PRS only makes sense if _SRS is implemented.

Change-Id: I030bd716215b5ac5738e00ebf6ed991d9d6c5ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69513
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17 21:20:50 +00:00
Arthur Heymans 148fd99365 superio/acpi/pnp_generic.asl: Add _PRS for each device
Simply return the current resource settings in the _PRS method. This
means that coreboot has to correctly set up the resources on the
device. This won't result in any regression as without _PRS the ACPI
OS would not know what resources settings are valid, so it would never
use _SRS.

Change-Id: I2726714cbe076fc7c772c06883d8551400ff2baa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64218
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-17 21:19:22 +00:00