Commit Graph

33241 Commits

Author SHA1 Message Date
Bill XIE 2e5f1f7e94 mb/hp: Add data.vbt files for folio_9470m and revolve_810_g1
Extracted from live running machines running vendor firmware.

Change-Id: I5082af9349c25a5f1759ba00b3fbf8d18f8fde4d
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:19:49 +00:00
Bill XIE 9594550452 ec/hp/kbc1126: Make firmware offsets user configurable
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.

This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.

Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 15:19:41 +00:00
Matt DeVillier 76ea54e962 mb/google/atlas: Add libgfxinit support
Add Kconfig, panel delays extracted from VBT (and confirmed by Linux)

Test: build/boot Atlas with libgfxinit and Tianocore payload

Change-Id: I94c227cd4f020db719bf81118d983493752bb00f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 15:18:17 +00:00
Matt DeVillier f41eea4c0c mb/google/peppy: Add Hynix memory HMT425S6CFR6A support
Adapted from Chromium commit b8dcb1a [Peppy: Update Memory IDs]

Add Hynix memory HMT425S6CFR6A support.
RAM_ID: 011 4GB Hynix HMT425S6CFR6A
RAM_ID: 111 2GB Hynix HMT425S6CFR6A

Original-Change-Id: I26d5c4ad00509e7823c325ee8391e0b18fee44d8
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1074849
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>

Change-Id: I4d165f61b8a13e5ed025e9ddbc4330db88e2fa3d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:18:05 +00:00
Matt DeVillier 66bd887005 mb/google/peppy: add _DSD to touchscreen ACPI
Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.

Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.

Test: build/boot peppy on 4.18+ kernel, verify touchscreen working

Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-31 15:17:51 +00:00
Meera Ravindranath 48c7870e52 soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.

Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).

Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-31 15:17:27 +00:00
Angel Pons 408d1dac9e mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-31 15:16:57 +00:00
Peichao Wang ae863e2e25 mb/google/hatch/akemi: modify DPTF parameters for new FAN
New FAN use NTN bearing, so tune DPTF parameters to satisfy
requirement

BUG=b:144370669
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6fbf0c80cd2421ce9a489c8923a97d860a11b545
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-31 15:15:26 +00:00
Elyes HAOUAS 959f406bf3 sb/i82801gx/nvs: Add missing <stdint.h>
Change-Id: I22b3fb31d8694c76b4a6fdfa40a72977e9099815
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37899
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 08:05:14 +00:00
Elyes HAOUAS 748caed022 northbridge: Add missing include <device/pci_def.h>
Change-Id: Ib63835d2407bbabbd78b43927f7fbd407ca06a08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37841
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 07:42:30 +00:00
Elyes HAOUAS 536799d5f6 sb/amd/cimx/sb800: Remove unused BOOTBLOCK_SOUTHBRIDGE_INIT
Change-Id: Ie0dc165076644e225064568b4cb6f73b2af66438
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-30 10:19:31 +00:00
Felix Held 734c999637 ibase/mb899: use common winbond/nuvoton HWM bank select function
Change-Id: I7f159074c25a0fdfe2ee15024c1ed6c062ce75d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30 02:57:37 +00:00
Felix Held 35103fd961 kontron/986lcd-m: use common winbond/nuvoton HWM bank select function
Change-Id: I169b16c99a864ecff54112bcc073f2c141c2009f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-30 02:57:28 +00:00
Felix Held 15b6c4af63 superio/nuvoton: add common HWM bank select function
Change-Id: I828b6caa37e52c13e1876c7ca4edbd171e70d3f7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37945
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-30 02:57:13 +00:00
Johanna Schander d756c27a54 util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29 21:13:17 +00:00
Felix Held 8fa02a8ef9 nb/intel/sandybridge: simplify ME lock and memory enable bit write
Timeless build results in identical image for X230.

Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29 12:20:16 +00:00
Felix Held bc3668a468 nb/intel/sandybridge: add and use defines for ME base and mask registers
Timeless build results in identical image for X230.

Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-29 12:19:43 +00:00
Felix Held 4902fee441 nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers
This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1

Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-29 12:19:14 +00:00
Rizwan Qureshi cf425783c8 ec/google/chromeec: ignore LIMIT_POWER based on command code in response
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.

BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.

Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-12-29 00:34:21 +00:00
Peter Lemenkov a76cf28279 mb/lenovo/*/acpi_tables: Don't initialize already initialized fields
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already.

Change-Id: I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-28 09:56:50 +00:00
Patrick Georgi 0acfe1c8cd util/testing: Remove romcc from testing
Change-Id: If90193dc7c85133b10082c68a6cec6c1b0b35ffb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37958
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-28 09:45:12 +00:00
Marshall Dawson 5b9062f3f6 soc/amd/common: Correct SPI FIFO size check
When checking that command and data fit in the FIFO, don't count the first
byte.  The command doesn't go through the FIFO.

TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550

Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-27 17:15:19 +00:00
Martin Roth 92bc83674b util/docker/coreboot-sdk: Add libcurl4 requirements for em100
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia1cd7e12f12cb6d26a10fd358a3b32c31ce1c834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-12-27 17:09:41 +00:00
Bora Guvendik d6db845f01 dram-spd: Remove free()
free() is not needed since the memory is not dynamically allocated.

Change-Id: I90659722aaca6ced1e1cbc3db4180b0811205e95
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-27 16:08:40 +00:00
Peter Lemenkov 9fadd9a917 mb/lenovo/*/acpi_tables: Don't zero out gnvs again
The gnvs structure was zeroed out already in the following files:

* src/southbridge/intel/i82801ix/lpc.c (t400 and x200)
* src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58)

Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-27 09:09:20 +00:00
Peter Lemenkov 6c2c018e15 mb/*/*/acpi_tables: Remove unnecessary function call
Remove acpi_update_thermal_table local function.

Change-Id: I4857348088feb8eaf1dd7f553c4efb29da8943cf
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27 09:09:02 +00:00
Paul Fagerburg 1fe7dcb047 util/mainboard/google: add support for Volteer
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.

kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.

BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.

$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template

$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template

Also run the script with an existing board name to verify that you
can't create a variant that already exists.

Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-27 09:03:48 +00:00
Seunghwan Kim f71991edc3 mb/google/kohaku: Update reset_delay_ms for digitizer device
We found the driver binding failure issue could be cleared with 100ms
of "reset_delay_ms". Needs further check with device vendor, anyway it
seems the IC need some time before communication after de-assertion of
reset.

BUG=b:129159369
BRANCH=firmware-hatch-12672.B
TEST=Verified driver bound successfully.

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-27 09:03:15 +00:00
Kyösti Mälkki d60e9ab74e cpu/intel/microcode: Apply more strict guard for assembly files
Change-Id: I8243be7c9a57402b2ac1cfa1c0552990d4a4ba74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-27 09:01:50 +00:00
Kyösti Mälkki 405812209d arch/x86: Remove <arch/cbfs.h>
There are no symmetrical headerfiles for other arch/ and
after ROMCC_BOOTBLOCK and walkcbfs() removal this file
ended up empty.

Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27 09:01:12 +00:00
Kyösti Mälkki 25c6d3a35f arch/x86: Remove walkcbfs()
This was used in romcc bootblocks.

Change-Id: Ie0cfbf124922d04a3320404d667610ad369ec00b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-27 09:01:03 +00:00
Arthur Heymans 945b698f82 util/romcc: Drop romcc support
Finally all boards use a GCC compiled bootblock!

Change-Id: I0c9a1b19dbdc32b43875da7d685718bae9d7f5f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37337
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 09:00:16 +00:00
Elyes HAOUAS c2092569d5 Makefile: Remove romcc
Change-Id: I2fe7fa8b23da3b909adc2b8bce59304acfb5b807
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-27 08:59:59 +00:00
Arthur Heymans efa56ab12b arch/x86: Drop ROMCC_BOOTBLOCK symbol
Change-Id: I968c4392849045cd50bfe2c83de44daba38ee245
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-27 08:59:32 +00:00
Kyösti Mälkki b8d575c644 bootblock: Support normal/fallback mechanism again
Change-Id: I7395e62f6682f4ef123da10ac125127a57711ec6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 08:59:20 +00:00
Wisley Chen 12b1d7df70 mb/google/hatch/var/dratini: Add a new sku for dragonair
Add a new sku for dragonair

BUG=b:146504217
TEST=emerge-hatch coreboot

Change-Id: I4492d65f35d3583df1606c5f2901228b3ae14e4a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-12-27 08:58:55 +00:00
Tim Wawrzynczak 0d9fb55ae2 ec/google: Fix wedging AP on early ec sw sync
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power
limits to reasonable defaults and can wedge the AP by browning out at
the end of vboot.

BRANCH=none
BUG=b:146165519
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 08:58:47 +00:00
Elyes HAOUAS f07d7dc2fd drivers/ipmi/ipmi_fru: Add missing <stdlib.h>
malloc() needs <stdlib.h>

Change-Id: I0cf6a5b76543cb6dac584de6628cfc459d5a60a8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37884
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 08:58:15 +00:00
Elyes HAOUAS d6de92ef1e src/include: Remove min/max() from <stdlib.h>
Change-Id: I9ded44422a267e244343502dd5d6ab355e5a788d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37378
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 08:57:44 +00:00
Elyes HAOUAS 2ad6f8138a mb/*/*/early_init.c: Remove defined but not used macro
Change-Id: I69c3b0b96fde8dc44a961c3d687f5aadbbdddde0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37644
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-27 08:56:43 +00:00
Idwer Vollering 7abc037da4 util/superiotool: alter Makefile to build the binary on FreeBSD
Change-Id: Ia96bee18abcdf278ae9178471cd4af2de454facf
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-26 22:06:18 +00:00
Matt DeVillier b5b8a7d540 nb/haswell/minihd: correct subsystem ID
The subsystem ID for Intel Mini-HD is always 0x80860101.

Change-Id: I74cbba31e93f9bb5b18d3ada780a0f24614ba029
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-26 19:05:14 +00:00
Matt DeVillier eafa2035ce soc/broadwell/minihd: correct vendor, subsystem IDs
Codec vendor ID was copy/pasted from Haswell, should be
0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101.

Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:55:02 +00:00
Eric Lai f107b6c3a0 mb/google/hatch: Clean up duplicate method
Moving Enable/disable GPIO clock gating to soc level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9be77908b4e44e08a707812fd8b23b23bcb56671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26 10:54:24 +00:00
Ren Kuo d4f39abebf mb/google/octopus/variants/dood: support LTE module
related LTE GPIOs:
  GPIO_67  - EN_PP3300
  GPIO_117 - FULL_CARD_POWER_ON_OFF
  GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
  - keep GPIO_67 and GPIO_117 high and
  - pull down GPIO_161 for 30ms then release it.

BUG=b:146843935
BRANCH=octopus
TEST=build and verify on the DUT with LTE

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26 10:53:52 +00:00
Sheng-Liang Pan b091b33c2a mb/google/octopus/variants/bobba: fix LTE power sequence and move
get_board_sku to smm stage.

fix Power_off section power sequence.
power_off_lte_module() should run in smm stage, add variant.c in smm stage.
also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage
and ramstage.

BUG=b:144327240
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-26 10:53:42 +00:00
Tommie 325fd3462e mb/google/octopus: Add two new sku IDs for foob
Declare these sku IDs:
    -SKU: 1 Foob, 1-cam, no touch, no pen.
    -SKU: 9 Foob360, 2-cam, touch, pen.

BUG=b:145837644
BRANCH=octopus
TEST=emerge-octopus coreboot

Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Iffcbb3f6f945ea299ff687a383a82b88dcd11ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2019-12-26 10:51:51 +00:00
Eric Lai 086f0faf75 soc/intel/cannonlake: Move GPIO PM configuration to soc level
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits.
Restore the PM bits when exit s0ix/Sx.

BUG=b:144002424
TEST=Check GPIO PM bits when enter/exit s0ix are expected

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-26 10:51:22 +00:00
Angel Pons a8ab2b33a4 Doc/tutorial/part2.md: Align headings with part1.md
Substitute `Part` with `Step` on this file's headings and use present
tense instead of gerund.

Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26 10:50:51 +00:00
Angel Pons 93b343a779 Doc/tutorial/part1.md: Fix minor formatting issues
Make sure all titles are capitalized, and add a missing period.

Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26 10:50:48 +00:00