Commit Graph

33241 Commits

Author SHA1 Message Date
Matt DeVillier 6343cd846a drivers/intel/gma: fold gma.asl into default_brightness_levels.asl
Including gma.asl at the platform level (vs the board level)
means that even desktop boards need to include the default
brightness levels, which makes no sense. To begin to clean this up,
include gma.asl in default_brightness_levels.asl (as well as
the handful of board-specific brightness files) and remove it
from the various platforms.

A follow-on commit will remove default_brightness_levels.asl
from all boards which lack an internal display.

Change-Id: I8063deeef4ab6d6ab34ed9b0be5b1d541d6e9b6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39878
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:51:33 +00:00
Duncan Laurie 14cf3245fe mb/emulation/qemu-q35: Enable CHROMEOS as an option
Allow Chrome OS to be enabled for this QEMU target.  By default
this does not change anything unless it is selected in the build
configuration, but it makes it possible.

Native VGA init is not forced when Chrome OS is enabled because the
drm-bochs driver does not work with chrome (even the latest upstream
kernel driver with drm atomic support) but it does work with virtio.
The coreboot graphics init needs to match what is selected with qemu
(with -vga std or -vga virtio) which in turn will determine which
kernel driver is used.

A second FMAP is added with both RW-A and RW-B regions which is
required by chromeos.

Recovery mode can be entered by supplying a custom fw_cfg option
when launching qemu: -fw_cfg name=opt/cros/recovery,string=1

Change-Id: I24b4532ea961e68558663292c99d121f0a30ce3b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31 10:47:26 +00:00
Duncan Laurie 516967c681 mb/emulation/qemu-q35: Enable option for TPM
This enables the mainboard to use a TPM if it is selected in the
configuration.  By default this does nothing, but it allows the
TPM to be enabled and used with the CONFIG_USER_TPM2 Kconfig option.

Using a TPM with QEMU requires either a physical TPM backend or
the swtpm package with a socket:

  -chardev socket,id=swtpm,path=/tmp/swtpm/socket
  -tpmdev emulator,id=tpm0,chardev=swtpm
  -device tpm-tis,tpmdev=tpm0

Change-Id: I0d79a5a0f590c57998ababb660b52d9e3ed2d484
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31 10:42:20 +00:00
Duncan Laurie b40e780f8b mb/emulation/qemu-i440fx: Add acpi_name handler for QEMU
QEMU does not have a separate northbridge chip, so the mainboard
needs to handle the ACPI name and paths so that devices can get
generated into the SSDT properly.  This fixes the PIRQ and TPM
table generation.

This issue can be seen in the coreboot output:
ACPI_PIRQ_GEN: Missing LPCB ACPI path

Change-Id: Ifc7d4359eea38ac0b55d655e39191ae7f8655fe4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31 10:41:32 +00:00
Duncan Laurie ddd4f9a717 mb/emulation/qemu-i440fx: Reserve low memory
Ensure that the low memory is properly reserved so it does not get
marked as normal RAM and get wiped or reused by firmware or the kernel.
This ensures that the low RSDP is always available for the kernel.

This is only noticed if something wipes the RSDP before the kernel
boots, which happens if you use the depthcharge payload and boot in
developer mode.

Change-Id: I7295018416229bc957ecbf26f77623a57965557e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-31 10:41:01 +00:00
Duncan Laurie 9f5c8503d1 mb/emulation/qemu-q35: Increase max size of ACPI tables
When the TPM is enabled in QEMU the fw_cfg interface will return
~200KiB of ACPI tables, so this needs to be increased from the default
in order to be able to boot.

This is seen when using a TPM with qemu as it will hang when
processing the fw_cfg tables.

qemu-system-x86_64 \
  -machine q35 -enable-kvm -vga virtio -serial stdio \
  -drive 'id=hd,file=disk.bin' -bios coreboot.rom \
  -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \
  -tpmdev 'emulator,id=tpm0,chardev=swtpm' \
  -device 'tpm-tis,tpmdev=tpm0'

Change-Id: I21980aace8e86e636f5ae7b55148f4c31404edba
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31 10:40:01 +00:00
Duncan Laurie f02bf35e00 arch/x86/tables: Move max ACPI table size to Kconfig
The maximum ACPI table size is currently hardcoded to 144 KiB.
When using QEMU with TPM enabled there is ~200 KiB of ACPI tables
returned by the fw_cfg interface, so in order to allow this to be
overridden by a mainboard move it to Kconfig.

This is seen when using a TPM with qemu as it will hang when
processing the fw_cfg tables.

qemu-system-x86_64 \
  -machine q35 -enable-kvm -vga virtio -serial stdio \
  -drive 'id=hd,file=disk.bin' -bios coreboot.rom \
  -chardev 'socket,id=swtpm,path=/tmp/swtpm/swtpm-sock' \
  -tpmdev 'emulator,id=tpm0,chardev=swtpm' \
  -device 'tpm-tis,tpmdev=tpm0'

Change-Id: Ib5baa8fe12cb9027a340875f1ccf5fef6f9460bd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-31 10:39:33 +00:00
Bill XIE 516c0a5338 security/vboot: relocate and rename vboot_platform_is_resuming()
After measured boot is decoupled from verified boot in CB:35077,
vboot_platform_is_resuming() is never vboot-specific, thus it is
renamed to platform_is_resuming() and declared in bootmode.h.

Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-31 10:38:07 +00:00
Bill XIE bad08c2c29 security/tpm: Include mrc.bin in CRTM if present
mrc.bin, on platforms where it is present, is code executed on CPU, so
it should be considered a part of CRTM.

cbfs_locate_file_in_region() is hooked to measurement here too, since
mrc.bin is loaded with it, and CBFS_TYPE_MRC (the type of mrc.bin) is
measured to TPM_CRTM_PCR rather than TPM_RUNTIME_DATA_PCR.

TODO: I have heard that SMM is too resource-limited to link with vboot
library, so currently tspi_measure_cbfs_hook() is masked in SMM.
Please correct me if I am wrong.

Change-Id: Ib4c3cf47b919864056baf725001ca8a4aaafa110
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-31 10:37:38 +00:00
Matt DeVillier ea861ce831 mb/51nb/x210: restore left USB3 port in devicetree
Was accidentially removed in 6e50849

Change-Id: I090b6bc8863d17412cb1e23ac816c39f479290c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39937
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:35:07 +00:00
Matt DeVillier 61ba3ac92e mb/google/slippy: Convert variants to use override devicetree
Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.

Test: build all slippy variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)

Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-31 10:34:42 +00:00
Matt DeVillier 98f609aad4 mb/google/link: Use GENERIC_SPD_BIN
Clean up Link's mainboard dir by putting the SPD files in
a spd subdirectory like all other/newer boards use, and
selecting GENERIC_SPD_BIN to include them in the build.

Test: build google/link and verify spd.bin unchanged

Change-Id: I9c2f9f77dbdd6552c5ae1e7a0df2051b9b85badc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-31 10:34:16 +00:00
Matt DeVillier 6269636418 mb/google/link: use default GMA display profile
Link's DID data makes no sense, and ACPI backlight controls don't work
as a result. Replace them with the default profile used by most/all
other boards.

Test: build/boot google/link, verify ACPI backlight controls functional

Change-Id: Ia7cb3f10bd3c05ebaf414c17a8f94d2e9b40ae26
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-31 10:33:58 +00:00
Elyes HAOUAS cfaf4c7ac8 superio/winbond/{w83627hf,w83977tf}: Use macro
Change-Id: I3ac8dd2ba089970a18b460769dfc3fabf9395709
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39907
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:33:10 +00:00
Wim Vervoorn 8602fb7f65 soc/intel/common/block/cse: Add check for CSE enabled
Exit print_me_fw_version if CSE is disabled.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: Ie3f1c2a5a7f96371a0da872efc3308850c382ba7
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-31 10:32:41 +00:00
Marcello Sylvester Bauer eff1306ea4 Documentation/mb/lenovo: Test shrunken ME on Ivy Bridge
Update the Lenovo Ivy Bridge documentation that no issues could be
observed on W530.

Tested on Lenovo W530 with stripped ME and found no issues:
commit 93b0c7cfc6

* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* mSATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* CPU temperature reporting
* Stress test stable (intel_pstate no_turbo due to W530 overheating bug)
  * Youtube videos
  * stress -c 8 -m 1 -t 3600

Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39603
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:32:25 +00:00
Bill XIE c79e96b4eb security/vboot: Decouple measured boot from verified boot
Currently, those who want to use measured boot implemented within
vboot should enable verified boot first, along with sections such
as GBB and RW slots defined with manually written fmd files, even
if they do not actually want to verify anything.

As discussed in CB:34977, measured boot should be decoupled from
verified boot and make them two fully independent options. Crypto
routines necessary for measurement could be reused, and TPM and CRTM
init should be done somewhere other than vboot_logic_executed() if
verified boot is not enabled.

In this revision, only TCPA log is initialized during bootblock.
Before TPM gets set up, digests are not measured into tpm immediately,
but cached in TCPA log, and measured into determined PCRs right after
TPM is up.

This change allows those who do not want to use the verified boot
scheme implemented by vboot as well as its requirement of a more
complex partition scheme designed for chromeos to make use of the
measured boot functionality implemented within vboot library to
measure the boot process.

TODO: Measure MRC Cache somewhere, as MRC Cache has never resided in
CBFS any more, so it cannot be covered by tspi_measure_cbfs_hook().

Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-03-31 07:55:18 +00:00
Evan Green 6b7bbc2b78 mb/google/kohaku: Add enable_delay_ms for wacom pen
Add an enable reset delay to avoid messages like this in the
kernel:

i2c_hid i2c-WCOM50C1:00: failed to change power setting.

This gets rid of all the warnings except one on reboot/shutdown.
That last case likely isn't fixed because the sleep command is
being sent directly from i2c_hid_shutdown(), so no ACPI routines
get to run and provide the delay. Since the machine is going down
for shutdown/reboot anyway, fixing that last case is a lower
priority.

BUG=b:145094539
TEST=Run on kohaku, switch to guest mode and log out, no errors

Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I8fadf497dd09e5b95b1d74443fb0543d3555dbb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-30 19:03:27 +00:00
Johanna Schander 8a6e036861 intel/fsp2_0: Make FSP_USE_REPO a SoC opt-in
For quite a bit now we are extending the FSP_USE_REPO option to be
available for all Intel SoCs. This results in a list being not only
hard to maintain but also prone to errors.

To change that behaviour this commit introduces the
HAVE_INTEL_FSP_REPO config option for SoCs that are supported from within
3rdparty/fsp.

If a SoC selects HAVE_INTEL_FSP_REPO the config option FSP_USE_REPO is
selected by default, but can be still deselected by the user in menuconfig.

Change-Id: I68ae373ce591f06073064aa75aac32ceca8fa1cc
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37582
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 10:53:51 +00:00
Ronak Kanabar e5565c45cb soc/intel/{icelake, tigerlake}: Remove DDI A lane programming
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.

BUG=b:150788968
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.

Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 09:42:55 +00:00
Angel Pons 991ee05de9 mb/gigabyte/ga-h61m-s2pv: rename to ga-h61m-series
It is not a single mainboard anymore, it's actually three variants.

Change-Id: I66f1239abadd8bf93269d6d4617329dc4b925e8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-30 08:55:19 +00:00
Angel Pons 0c0b16ac9e mb/gigabyte/ga-h61m-*: Use overridetrees
Make use of overridetrees, as these mainboards are very similar.

Tested on GA-H61MA-D3V, still works fine.

Change-Id: I1b587a091da631cb172eb76722958da6c7518893
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39668
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 08:54:30 +00:00
Elyes HAOUAS 95cdd9f21b nb/intel/i945: Make some cosmetic changes
This will make i945GC and i945GM splitting easier.

Change-Id: I3acc1f526056248f8fbb1778a3c381d369faf020
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30 08:50:50 +00:00
Peter Lemenkov 98b78efabe mb/lenovo/t530: Switch to overridetree
Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30 08:48:13 +00:00
Keith Hui 7e269ad06c asus/p2b-f: Transform into variant
TEST=build with BUILD_TIMELESS=1, binary does not change

Change-Id: I56983cabfad574b970aba098a178e691c6b354d1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30 08:47:36 +00:00
Keith Hui bf7d6f1a82 asus/p2b: Transform into variant-enabled structure
Get ready to squash all the ASUS i440BX boards together.

Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30 08:47:21 +00:00
Angel Pons 0a9650c1d4 mb/gigabyte/ga-h61m-s2pv: Correct PCIe port setup
Coalescing is not needed, as root port #1 is enabled. Also, update the
comments to look more like the other two variants. Note that the Intel
H61 PCH only has six root ports, so devices 1c.6 and 1c.7 do not exist.

Change-Id: I3f4bf99ceec6c77f6e1eabea9b712245afee7d34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39742
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 08:46:17 +00:00
Furquan Shaikh 1908340b69 memranges: Change align attribute to be log2 of required alignment
This change updates the align attribute of memranges to be represented
as log2 of the required alignment. This makes it consistent with how
alignment is stored in struct resource as well.

Additionally, since memranges only allow power of 2 alignments, this
change allows getting rid of checks at runtime and hence failure cases
for non-power of 2 alignments.

This change also updates the type of align to be unsigned char.

BUG=b:149186922

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie4d3868cdff55b2c7908b9b3ccd5f30a5288e62f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-30 08:44:53 +00:00
Furquan Shaikh f79f8b4e33 helpers: Add a helper macro for calculating power of 2
This change adds a helper macro POWER_OF_2 that is useful for
calculating the requested power of 2.

Change-Id: Ie70f93b6ac175699c11cae7d8f023a52cce01e88
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-30 08:44:33 +00:00
Tim Wawrzynczak 654d9d6b36 mb/google/deltaur: Provide initial devicetree
This initial devicetree attempts to correctly configure the status of
each PCI device. Not all required drivers are instantiated, nor are
all of the SoC options fully selected yet.

PCIe root ports are enabled and clocks are assigned.
USB ports are assigned.

BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30 08:43:46 +00:00
Tim Wawrzynczak d8bff383c2 mb/google/deltaur: Add initial GPIO configuration
This configuration sets up all of the GPIO pads for the first rev of
the board.

BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30 08:43:32 +00:00
Bora Guvendik 3a1a037231 mb/google/deltaur: add deltaur mainboard initial support
Created a new Google baseboard using Tiger Lake named deltaur, taking
volteer as a starting point.

BUG=b:151102807
TEST=make build successful

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-03-30 08:43:09 +00:00
Martin Roth 97bd2a7f33 soc/amd/picasso: Add helper functions for finding SOC type
We're running into more and more situations where we need to tell one
SOC type from another, and instead of rewriting them every time, just
add some helper functions to the picasso SOC directory.

Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/2051514
Reviewed-on: https://chromium-review.googlesource.com/2060904
Reviewed-on: https://chromium-review.googlesource.com/2060905
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30 08:42:02 +00:00
Brandon Breitenstein 91dddd47b3 tgl boards: Configure retimer Aux orientation
In order to create a working baseline all ports are being set to have
retimers. Setting the TcssAuxOri UPD to 0 in order for the SoC to not
misconfigure the ports. Volteer will need some additional changes after
this is implemented to account for ports that do not have a retimer.

This setting is in the process of being documented in the TGL EDS and we
can update once it is fully understood what this setting is changing on
the SOC side.

BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on Volteer,
Connecting Type-c display should work regardless of Type-c cable
orientation.

Change-Id: I29eb0513299126ad8d1ee11ded2c771f28ad13f3
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39460
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 08:41:37 +00:00
Brandon Breitenstein fc932374a2 soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3.
Configure TcssAuxOri to retimer enabled on the port 2 Type-C port.
This setting informs the SoC that a retimer is taking care of SBU
orientation therefore it does not need to do any flipping.

The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux
orientation settings for the Type-C ports. The TGL EDS describes this
setting and what each bit represents.

Reference section 3.6.5 in TGL EDS #575681
BUG=b:145943811
BRANCH=none
TEST=Boot to OS and check Type-C port1 Display on volteer,
Connecting Type-C display should work regardless of Type-C cable
orientation.

Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 08:40:45 +00:00
Frank Wu bc83738301 volteer: Create halvor variant
Create the halvor variant of the volteer reference board by copying the
template files to a new directory named for the variant.

BUG=b:151399850
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_HALVOR

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: If4d3417ba55d56af441c99d949a196328d7a1951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-30 08:40:16 +00:00
Aaron Durbin d47afe90ef util/sconfig: emit NULL sibling fields
It's helpful to see the sibling field, even when it's NULL, when
debugging the static.c output from a devictree.cb file. Ensure the
NULL fields are emitted for fullness.

Change-Id: Ib6d5b8164769a6512e762d5a525c7df1f429c866
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-30 08:37:56 +00:00
Shaunak Saha d72cca0c44 mb/tglrvp: Add GPE configuration
Update the GPE configuration for dw0, dw1 and dw2.

BUG=None
TEST=build and boot tglrvp

Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30 08:37:39 +00:00
David Wu 1e40a11577 mb/google/hatch/var/kindred: set wifi sar for kled
Enable wifi sar feature and set wifi sar name for kled sku.

BUG=b:152277272
TEST=emerge-hatch coreboot chromeos-bootimage and
     verify wifi SAR load by sku-id

Change-Id: I9ee242773fd05cc2bcd7bde07da8176022827677
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-03-30 08:37:14 +00:00
Matt DeVillier 5d841e6a17 mb/google/glados: disable serial console by default
Glados boards do not have an exposed serial port outside
of the servo interface. Set board Kconfig so that a default
built image with Tianocore payload is bootable and doesn't
hang due to trying to send data over a non-existant serial port.

Test: build/boot google/chell with board defaults

Change-Id: Ifad6f805e66438e2c436d9fa235d9be2ecf69179
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-29 18:16:29 +00:00
Nico Huber b0b25c8e9c drivers/intel/gma/acpi: Provide default definition for displays
Use it wherever the standard numbers were copied to. Bit 31 is set
at runtime unconditionally, so we don't need it here.

Change-Id: I0d853c3b8250a2c7b2d1a91985a555e4b17ad76c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39731
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29 18:10:50 +00:00
Nico Huber 9af0b15e95 drivers/intel/gma: Drop unused `backlight` field
Change-Id: I9d7f8337653f93f40550a3d2886fe7b3845eac69
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29 18:03:47 +00:00
Nico Huber c2e46420cc nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside
configuring the PWM frequency in Hz, we also use the PCH's logic
for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux
would toggle it anyway and that might confuse our ASL code.

We assume that the 183Hz value that was set before for Slippy
variants was overridden by Linux with the 200Hz VBT value, like
it was for the Broadwell Chromebooks. So we set 200Hz for them
in the devicetrees. The calculated value for the T440p of 220Hz
seems sane and also matches the VBT.

Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29 18:03:30 +00:00
Matt DeVillier 8107c81e07 src/device/Kconfig: Adjust Graphics init defaults
Adjust the defaults for Graphics Initialization so
that the "best" option for a board is selected by default.
Net effect is to select RUN_FSP_GOP over VGA_ROM_RUN
in cases where the platform supports GOP init and the
mainboard has a VBT file included.

Test: run 'make menuconfig' and check default Display
Init option for google/cyan, observe RUN_FSP_GOP is default.

Change-Id: I2184dbdd943d035d1682b3ae7bd8d005221434b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-29 18:01:37 +00:00
Matt DeVillier de349ed45c mb/google/cyan: Clean up Kconfig
Cyan has no VGA BIOS available (at least not publicly), so
remove related options. Disable SoC serial output by default,
since no production devices have this exposed, but leave it
as a user option so it can be selected as needed (eg,
for use with a Google debug servo).

Change-Id: Ic079a39ca5ad0ac653b52248244b94d4bfbd08a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39872
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29 18:01:18 +00:00
Matt DeVillier 044b49c381 mb/google/glados: remove Chrome-EC defaults
Chrome-EC/PD images for all glados variants need to be built
from the board-specific branch, not master. Including the default
board names serves no purpose and requires users to deselect
the "use built-in EC firmware" in order for the board to build.

Test: build google/chell with defaults

Change-Id: Ic10f11337b85035068cdc4fe8147413e6b7f57ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29 18:00:58 +00:00
Matt DeVillier 6e50849b8c mb/51nb/x210: Fix up USB ports in devicetree
Add missing port definition for the mSATA/WWAN mPCIe port,
set OC pin for internal ports to OC_SKIP, fix port
descrption for mPCIe/WLAN port, remove USB3 definition for
right type-A port as it is USB2 only.

Test: insert WiFi module into WWAN port, observe BT portion
detected and functional.

Change-Id: Ie39b99eeb0f605ff07d57c32189fb1f4183713e4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29 18:00:20 +00:00
Arthur Heymans b49e210984 cpu/x86/Makefile.inc: Fix external toolchain build
The sipi_vector.S just needs to be linked as relocatable
so there is no need to invoke the compiler.

TEST: BUILD_TIMELESS=1 has the same hashes

Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-29 17:52:46 +00:00
Paul Fagerburg 4554942c8c hatch: Create sushi variant
Create the sushi variant of the hatch reference
board by copying the template files to a new directory named
for the variant.

(Auto-Generated by create_coreboot_variant.sh version 3.0.0).

BUG=None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SUSHI

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-03-29 17:51:41 +00:00
Martin Roth eb30e1a9aa soc/amd/picasso: Add and use CPUID defines for Picasso and Raven2
Change-Id: I35a1c404ff2f381d3d6bf4f2e4bbbf5429db38c3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1961485
Reviewed-on: https://chromium-review.googlesource.com/2060905
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-29 15:33:20 +00:00