Commit graph

15936 commits

Author SHA1 Message Date
Mario Scheithauer
6438084eab mb/siemens/mc_ehl2: Adjust PSE TSN settings in devicetree
This mainboard uses all three internal Ethernet GbE-TSN controllers. Two
of them are initialized by the Programmable Services Engine (PSE).

This patch enables the Serial Gigabit Media Independent Interface
(SGMII) mode for GbE PSE0 and GbE PSE1. By setting PCH PSE DMA pins to
host owned, the IO is under control of the IA processor cores through
system software.

TEST:
- Boot mc_ehl2 into Linux and check inet addr via 'ip a'

Change-Id: I74e660548b2c44d5dbdb6023d5a36cfdd7e96f43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-05-16 13:23:05 +00:00
Raihow Shi
bd192821bb mb/google/brask/variants/moli: remove DB_OPT from overridetree
Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is just physically remove option board from motherboard,
so it just need one vbt, and it don't need the fw_config to decide
which vbt will be return.

BUG=b:231769131
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1f8cdcbc05ed3bc689d29261e4fd4d700326dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 13:20:28 +00:00
Raihow Shi
cc115cb71a mb/google/brask/variants/moli: return the default VBT
Both option-HDMI and option-DP use the same setting of vbt,
and ABSENT is physically remove option board from motherboard,
so set default vbt has option-DP setting and only return it.

BUG=b:231769131
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I440143dabcf04c103f2a4420a7e4afb8ec12ec1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 13:20:13 +00:00
Felix Held
5481eb3c2e mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig
Use the existing definitions from FspUsb.h instead of magic values for
the ComboPhyStaticConfig settings in the mainboard's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 12:28:46 +00:00
Kyösti Mälkki
8a80cc8dd0 google/cyan: Clean up write_protect_state()
The commentary was wrong, write_protect_state() is only called
in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is
selected.

Implementation of get_gpio() eventually does the MMIO read, so
BOARD_GOOGLE_CYAN was not a special case.

Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16 07:03:31 +00:00
Tim Wawrzynczak
159520ed78 mb/google/brya: Consistently put void before __weak attribute
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 05:20:40 +00:00
Reka Norman
48e16f76c5 mb/google/nissa/var/nivviks: Disable PCIe WLAN pins
Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs.

BUG=b:218929856
TEST=Boot to OS on nivviks and check that WLAN still works.

Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:11:29 +00:00
Reka Norman
f2f785dbbe mb/google/nissa/var/nivviks: Add support for NVMe and UFS
Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are
only supported on nirwen, an additional nissa variant based on nivviks
and sharing the nivviks coreboot target.

BUG=b:218929856
TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS
will be tested once nirwen boards are available.

Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:11:07 +00:00
Reka Norman
e4ebc86a3b mb/google/nissa/var/nivviks: Update GPIOs to support nirwen
Nirwen is an additional nissa reference board which is almost identical
to nivviks, so is reusing the nivviks coreboot variant. However, there
are two GPIO changes, so update the GPIO tables to handle these based on
board_id.

nivviks:
GPP_D6  -> WWAN_EN
GPP_E13 -> NC

nirwen:
GPP_D6  -> SSD_CLKREQ_ODL
GPP_E13 -> WWAN_EN

BUG=b:218929856
TEST=Boot to OS on nivviks

Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:52 +00:00
Reka Norman
1c7f9f914d mb/google/nissa/var/nivviks: Disable pen garage based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen
garage is enabled/disabled as expected.

Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:39 +00:00
Reka Norman
f1b8cee5f3 mb/google/nissa/var/nivviks: Disable MIPI WFC based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC
is enabled/disabled as expected.

Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:11 +00:00
Usha P
49df3cff0d mb/google/brya: Remove Rcomp resistors override for Nissa
This patch sets the RComp resistor values to default values needed.

BUG=b:231202733
TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set
to default values from debug FSP log.
[SPEW ]  Updating Rcomp Targets:
[SPEW ]   RcompTarget[RdOdt]: 48
[SPEW ]   RcompTarget[WrDS]: 30
[SPEW ]   RcompTarget[WrDSCmd]: 20
[SPEW ]   RcompTarget[WrDSCtl]: 20
[SPEW ]   RcompTarget[WrDSClk]: 20

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2c7a54c49e282446ece77ca406951782282a009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16 05:06:19 +00:00
Terry Chen
62d3ba808d mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota.

BUG=b:231686917
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16 05:03:53 +00:00
Terry Chen
37ffdf3d5c mb/google/crota: Change ELAN touchscreen i2c address and HID
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C

BUG=b:231684121
TEST=local build and tested with ELAN touch screen

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ide005a0681e236c3102090c1c36ab81926849000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16 04:55:12 +00:00
Reka Norman
baf22462b7 mb/google/nissa/var/nivviks: Disable SD card based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD
card is enabled/disabled as expected.

Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 04:51:27 +00:00
Reka Norman
d88233ecd3 drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15
Ti50 firmware versions below 0.0.15 don't support the firmware_version
register and trying to access it causes I2C errors. Some nissa boards
are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading
the firmware version and select it for nissa. The firmware version is
only read to print it to the console, so it's fine to skip this. This
workaround will be removed once all ODM stocks are updated to 0.0.15 or
higher.

A similar workaround Kconfig was added in CB:63011 then removed in
CB:63158 which added support for separate handling of Cr50 and Ti50.
But we actually still need this workaround until all Ti50 stocks are
upgraded to 0.0.15 or higher.

BUG=b:224650720
TEST=Boot to OS on nereid with Ti50 0.0.14

Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16 04:51:13 +00:00
Eric Lai
6cb787b19a mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIO
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need
to set it as INT in coreboot to make the IRQ work.

BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16 04:51:04 +00:00
Felix Held
221c15d3a0 mb/amd/chausie/devicetree: add USB PHY configuration
Specify the USB PHY settings in the devicetree instead of relying on the
FSP defaults. The USB PHY configuration for Chausie are taken from the
internal UEFI code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16 04:39:26 +00:00
Stefan Ott
0d943175f1 mb/lenovo/t60: Add support for ThinkLight
With this patch, the ThinkLight on the ThinkPad T60 can be controlled
through the OS.  This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.

After applying this patch, the light can be controlled like this:

    echo on >/proc/acpi/ibm/light
    echo off >/proc/acpi/ibm/light

Or through sysfs at /sys/class/leds/tpacpi::thinklight

Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16 04:38:08 +00:00
Elyes Haouas
db735c478e src: Remove unused <cf9_reset.h>
Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"

Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:40:14 +00:00
Elyes Haouas
a618e11f1a mb/{google,ocp}: Remove unused <bootstate.h>
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:39:32 +00:00
Elyes Haouas
386e8494bb mb/google/stout: Use pci_update_config32()
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie1d2965b384e5653958f7f8503c62b8a16fa7bc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:35:10 +00:00
Elyes Haouas
c9b219804b mainboard/amd/padmelon: Use pci_or_config32()
Change-Id: I8d55fc93f6ec413d0cbcea2f8e0a90a76f1803cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:29:58 +00:00
Arthur Heymans
2888c80f26 mb/google/eldrid: Fix use of float
Floats are not allowed in coreboot.
As the compiler rounded down the value, do so in the code too as this
is a known good value.

Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-14 14:19:17 +00:00
David Wu
305086c0f2 mb/google/brya/variants/osiris: Init devicetree for osiris
Init basic override devicetree based on schematics

BUG=b:224423318
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13 15:47:23 +00:00
David Wu
f5319efa84 mb/google/brya/variants/osiris: Configure GPIOs according to schematics
Update initial gpio configuration for osiris

BUG=b:224423318
TEST=FW_NAME=osiris emerge-brya coreboot

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-05-13 15:47:11 +00:00
Arthur Heymans
522c92ed35 mb/google/glados: Fix unused variable
Commit f89cb241ee introduced a regression where the RcompTarget was
not updated according to the SPD.

Change-Id: I07715224b11937604b107e370d957745b245ddd9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13 11:00:59 +00:00
Ian Feng
7066f1575e mb/google/skyrim: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:230682161
TEST=manual test on Skyrim:
Volume Up/Down and Power buttons, Tablet Mode switch

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-05-12 19:45:26 +00:00
Tim Wawrzynczak
da958d679d mb/google/deltaur: Remove mainboard from tree
This board never made it to production, and development on it has long
since stopped; it is a maintenance burden, therefore drop it from the
tree.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-12 19:41:48 +00:00
Yu-Ping Wu
05f2ff98c6 mb/google/corsola: Enable TPM_GOOGLE_TI50
Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50.

BUG=b:232066387
TEST=emerge-corsola coreboot
BRANCH=none

Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12 18:42:07 +00:00
Karthikeyan Ramasubramanian
a2bba5b5f1 mb/google/skyrim/var/skyrim: Add USB WWAN configuration
Add Fibcom FM101-GL USB WWAN configuration with the required power
sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0.

BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is
enumerated in the output of lsusb.
localhost ~ # lsusb
Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12 18:40:18 +00:00
Karthikeyan Ramasubramanian
d52adc4a87 mb/google/skyrim/var/skyrim: Add VL822 USB hub
In Skyrim, USB-A port and WWAN modules are connected to the SoC USB
ports through an external hub. Update the USB configuration in the
devicetree accordingly. Enable the ACPI driver for external USB hub.

BUG=b:227761300
TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports
are enumerated correctly in the output of lusub command.

Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12 18:40:07 +00:00
Raihow Shi
bcec2904c8 mb/google/brask/variants/moli: Set GPP_E14 as the default value.
We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14
as the default value to let HDMI-DDIA get hot plug detection.

BUG=b:231769129
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12 18:36:37 +00:00
Tyler Wang
8adcdb3abb mb/google/nissa/var/craask: Add supported touchpad
Add related settings for synaptics touchpad.

BUG=b:229938024
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-12 18:36:16 +00:00
Sean Rhodes
b608db9ef5 mb/starlabs/labtop: Enable Max Charge for CML
Enable the max charge feature for cml, as the EC supports it since
Star Labs EC firmware 1.06.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I779a686960b63025fb5f40e826ed117f402a0b2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12 18:34:04 +00:00
Tony Huang
1ffec679fe mb/google/brya/var/agah: Enable PCIe RP 3 for LAN
Using CLKREQ 4 and CLKSRC 4

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-12 18:33:16 +00:00
Arthur Heymans
8ceef408e7 soc/amd/*/Makefile.inc: Do some cosmetics
The first target for the add_intermediate targets is always
$(obj)/coreboot.pre.

Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-12 11:12:31 +00:00
Scott Chao
a0cd3ee966 mb/google/brya/var/crota: enable wifi sar
BUG=b:216594621
BRANCH=brya
TEST=build pass and SAR table be changed according to tablet/ desktop mode

Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11 15:02:54 +00:00
Dtrain Hsu
7886d46316 mb/google/brya/var/kinox: Disable thunderbolt interface
Disable all of the TBT devices in devicetree since kinox doesn't support
thunderbolt. The change also need to disable TBT in fitimage
(chrome-internal:4731094).

BUG=b:231654363
TEST=Build and run on DUT.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11 15:00:56 +00:00
Casper Chang
8f6fd32648 mb/google/brask/variants/moli: correct tcss_usb3 port
Correct tcss_usb3_port to meet Moli's schematic design.

BUG=b:220814038
TEST=emerge-brask coreboot

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11 14:34:25 +00:00
Arthur Heymans
cc70646255 *.h: Fix up typos in guarding
Clang complains about this.

Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63067
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-11 06:04:10 +00:00
Arthur Heymans
a74504b729 mb/*/bootblock.c: Fix set but unused variable over inb loop
Change-Id: Iba80c4a5960c6fb59f542b33e8e769576ccfed59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-05-11 06:01:59 +00:00
Casper Chang
eb8bbb6c04 mb/google/brask/variants/moli: enable BT offload
Enable BT offload of NAU88L25B on Moli with fw_config NAU88L25B_I2S.

BUG=b:220814038
TEST=emerge-brask coreboot,
     Check BT offload enabled in CPU log and audio works.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I72d91d2dafffa7d9604b7dd3d697cb3b2b04b152
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06 21:56:37 +00:00
Terry Chen
3d51519685 mb/google/brya/var/crota: Fix codec reset pin in overridetree
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the
reset pin to be deasserted in ramstage for proper power sequencing.

BUG=b:230074351
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06 19:34:05 +00:00
Stephen Edworthy
0405d8b3ef mb/starlabs/lite: Change PMC from hidden to on
With the PMC set to hidden, on certain Operating Systems,
including ZorinOS 16 and Manjaro 21.2.5, it would get stuck
at a black screen when exiting from S3.

With the PMC set to on, this issue no longer occurs.

Signed-off-by: Stephen Edworthy <stephen@starlabs.systems>
Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-05-06 16:45:19 +00:00
Raihow Shi
8e14df3b6f mb/google/brask/variants/moli: disable ASPM on pcie_rp 6
Currently coreboot will hang on ASPM on pcie_rp 6,
so disable ASPM to let it go into kernel.

BUG=b:231400217
TEST=emerge-brask coreboot.

Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I79a80d97d168f40e58774e5652967d659daa323c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-06 13:38:02 +00:00
Terry Chen
c8a986d14c mb/google/brya/variants/crota: Enable Bluetooth offload support
Enable CnviBtAudioOffload UPD from Intel Guideline

BUG=b:230418589
TEST=emerge-byra coreboot and verified pass

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06 13:37:32 +00:00
Angel Pons
da4e1d7806 soc/intel/tigerlake: Add enum for DdiPortXConfig
Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.

Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-05-05 17:38:14 +00:00
Gaggery Tsai
bd9cec8ae5 mb/google/brya/var/vell: Remove unused i2c7 settings
This patch removes unused i2c7 settings. Accroding to EVT schematic,
i2c7 is reserved for AMP but resistors are unstuffing.

BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
     && checks EC log and ensures the DUT could enter s0ix.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05 17:37:10 +00:00
Teddy Shih
405c73005f mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a
Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects
EC of I2C 5 bus and GPIO D22, D23, as well  as, SoC of GPIO E11, refer
to mainboard schematic.

BUG=b:213549229
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: If172d13aa62503547227adf91f049ea50b948888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05 16:06:40 +00:00