This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Crota360 is using a Cirrus CS42L42 for its audio codec; it
requires the reset pin to be deasserted in ramstage for proper
power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Functions that are intended to override weak ones defined in the
baseboard should not also be declared weak, otherwise how would
the linker know which copy to keep.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add entries to the devicetree override for brya0 and enable the Kconfig
to ensure the Chrome OS EC Mux driver is build tested.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use common ASL defines for POST code handling.
Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.
Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Align POST code ASL elements with existing code in newer southbridges.
The main differences are that `NoLock` is changed to `Lock`, and that
names have been changed. The lock type change should not be a problem
because the field is only used once in the _PTS method.
Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Per Microsoft's spec for HID over I2C [1], interrupts must be level
triggered. Switch GPIOs and the devicetree config to conform to this.
Touchpad and multitouch gestures were already working, so no behavior
changes are observed in normal use.
[1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.
Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.
BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
Nereid.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch enables TBT PCIe root port 3.
BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
ensure 07.3 is in the list.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Read the EEPROM to detect the DDI type.
BUG=b:225139014
TEST=Boot chausie and correctly detect display card type
Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for the chausie EC. Use EC to configure default board GPIO
settings.
Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Chausie uses the spi1 pads for eSPI
Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()"
significantly reduced the size of the bootblock. This makes the space
saving options, required to make to bootblock fit in the 32K SOC
limit, unnecessary.
TESTED: with configs/config.google_octopus_spi_flash_console the .text
size is 0x29c8 bytes which is still well below the 0x8000 SOC limit.
Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This area is used for storing AP RO verification data.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout
BRANCH=none
Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The unit of dram speed is MT/s so append it on variable name.
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
- enable CPU PCIe VGPIO for PEG60
- enable GPP_C3/ GPP_C4 native function
- set unused GPIO to NC
BUG=b:229584785
BRANCH=none
TEST=build and boot into kernel v5.10
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.
BUG=b:229549930
BRANCH=none
TEST=build and pass memory training
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
BUG=b:229547171
BRANCH=none
TEST=pass memory training with error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If6acf8cb9474f816374743fd1e800da46958993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Camera LED flicker 3 times or so as sensor is being probed
during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot preventing camera LED flicker.
Corrects that by explicitly sequencing the reset GPIO and power GPIO
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flickers
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set native function (SD_AUX_RESET_L), and drive it high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We need to include the SMM handler to enable SCI events when ACPI is
enabled.
With this enabled we now see we have EC timeout problems while in SMI:
[SPEW ] SMI# #1
[WARN ] SMIx88 => 0x800
[DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG] Chrome EC: UHEPI supported
[ERROR] Timeout waiting for EC QUERY_EVENT!
[DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
[ERROR] EC returned error result code 1
[DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb
We still need to debug that. I suspect we have problems reading from
the ACPI IO decodes 0x62 or 0x66.
BUG=none
TEST=Verify SMI handler runs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.
BUG=b:227282870
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CONFIG_ONBOARD_SAMSUNG_MEM is not used anymore.
Remove CONFIG_ONBOARD_SAMSUNG_MEM.
This patch was intended to be part of CB:59754, but was not included in
the latest patchset.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: Id351bcafe005cc1b3319d7186ece2b5b9a7f49ac
Signed-off-by: Frans Hendriks <fhendriks.eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
There is a firewire chip TSB43AB22A mounted on the PCI bridge.
Add its definition to the device tree and mention it in the comment.
Change-Id: Iaa702b1efc15818ade2b1cd15aa6d415c3850e4b
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some devices/settings doesn't have helpful description in comments.
Update comments to describe the physical device on the board.
Change-Id: I479f41d71342104e74f862cf37b967963bc54877
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The current configuration is masking off IRQ 1 and IRQ 12 to the PIC.
This for some reason causes problems when using level triggered
interrupts. This change updates the PIRQ_MISC0 value to match what
skyrim is doing. This will enable level interrupts to work correctly.
BUG=b:218874489, b:160595155
TEST=Boot zork and verify keyboard still works. Boot with patch train
and verify keyboard works as expected.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Create the mithrax variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:223091246
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MITHRAX
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
A new iteration of Google's TPM implementation will advertize a new
DID:VID, but otherwise follow the same protocol as the earlier design.
This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50
to be able to take slightly different code paths, when e.g. evaluating
whether TPM firmware is new enough to support certain features.
Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The front status LED on the Librem Mini is driven by the SATALED# GPIO
line configured for native function, so only shows disk activity for
SATA drives, but not NVMe. To allow it to show disk activity for NVMe
drives as well, reconfigure the GPIO as GPIO-OUT (rather than native
function), and configure it via ACPI so that the linux gpio-leds
driver will attach and use it accordingly.
This has the added benefit of allowing the user to reconfigure the
LED as they see fit via sysfs.
Test: boot Linux (PureOS) on Librem Mini v2 with NVMe drive, observe status
LED blinks during periods of disk activity (tested via 'stress').
Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:227165770
TEST=build FW and system power on.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add WiFi SAR table for taniks.
BUG=b:226690925
TEST=build FW and checked SAR table can load by WiFi driver.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
commit c6b041a12e refactor the TPM Kconfig. MAINBOARD_HAS_LPC_TPM
has changed to MEMORY_MAPPED_TPM.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.
BUG=b:213403891
BRANCH=guybrush
TEST=Build and boot to OS in Dewatt board version 3.
Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing
the PSP to hang when resuming from S0ix suspend. The root cause is still
under investigation. Just disabling PSPP fixes the hang but causes poor
PLT performance.
BUG=b:228830362
BRANCH=guybrush
TEST=suspend_stress_test on AC and DC
Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alder Lake-N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.
Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.
BRANCH=NONE
TEST=Build and boot ADL-N RVP.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2ecc3018a1ab039990ba47898ff0e0e2ede695cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62913
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.
BUG=b:226684990
TEST=emerge-brya coreboot
Cq-Depend: chrome-internal:4676926, chrome-internal:4686953
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I9852553f5c91494db845d45a94e2566248538bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
MT53E512M32D1NP-046 WT:B (Micron)
MT53E1G32D2NP-046 WT:B (Micron)
H54G46CYRBX267 (Hynix)
H54G56CYRBX247 (Hynix)
K4U6E3S4AB-MGCL (Samsung)
K4UBE3D4AB-MGCL (Samsung)
BUG=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the osiris variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:229352299
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OSIRIS
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I41e088a3415add86cba87c919af23494f816bb24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The
default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:228929196
TEST=emerge-brya coreboot and pass RF test as before
Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The PCI Local Bus Specification Revision 3.0 requires that
multi-function devices always implement function 0. Because of
this, enabling UFS (PCI device 12.7) requires ISH (PCI device 12.0)
to be enabled as well.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia8b9561973640edc5f7d0f579dd640e805c0af17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, this CL enables both
the UFS controller and ISH.
TEST=Boot to kernel and check lspci output
00:12.0 Serial controller: Intel Corporation Device 54fc
00:12.7 Mass storage controller [0109]: Intel Corporation
Device 54ff
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62662
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit d80d88c0fe.
Reason for revert: 100Mhz should only be enabled on DeWatt
on board version >=3. Enabling it on board version 2 will
cause failures.
BUG=b:213403891
BRANCH=guybrush
TEST=Build dewatt
Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.
Change-Id: If56267e8a68897236d5ff73322317cbef7ab2243
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.
Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.
Change-Id: I7e702e9318fbf68dbd883a145111e6beb6815b8b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.
Change-Id: Ic37608ac9622b37cae6d81045740a033e9aa9d4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This should no longer be needed because the ASL has been fixed.
Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two
mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`.
Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only
mainboard using the SCH5545 code, `dell/snb_ivb_workstations`.
Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `_PRS` ACPI object is not needed for static (non-configurable)
devices. For devices where `_CRS` always provides the same set of
resource settings, drop the `_PRS` object. Note that every dropped
`_PRS` object only provides one set of resource settings, which is
identical to the resource settings provided by the `_CRS` object.
The no-op `_DIS` methods can also be removed for the same reason.
Also, drop `IGNORE_IASL_MISSING_DEPENDENCY` as it's no longer needed.
Change-Id: I71275f2581b999d606f36773578b36dbdccf6452
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
1. Remove dmi.h as it's migrated as gpmr.header
2. Remove unused gpmr definitions
3. For old platforms, define DMI defintions in c code
for less code changes.
TEST=Build
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This alias name is required for the mainboard.c code to generate the
appropriate power-off seqeuence for use during orderly S5 shutdown
from the OS. It had been accidentally removed, but is required, so
this patch adds it.
BUG=b:227788351
TEST=compile
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Disable SATA config from devicetree for ADL-N RVP, since we are not
planning to use it in chrome config.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ic9dce3a0b06e1a0d0d9fa495aa406eb12557d842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.
BUG=b:213403891
TEST=Build and boot to OS in Dewatt board version 2.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add conn1 for pch_espi and add type-c port2 for pmc_mux.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence,
the reason is that the rise and fall times of each signal
may differ by board, and so those board-specific delays
must be taken into account when power sequencing.
We checked power on sequence requires enable pin prior to reset pin,
so added delay to meet the sequence.
Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:228907551
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove i2c1 because brask devicetree is already has it.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable pen garage. Pen detect is active low.
BUG=b:229168203
TEST:Build and boot to OS in skyrim. Evtest work as expected
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649922170.578779, -------------- SYN_REPORT ------------
Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add Goodix touchscreen according to the Programming Guide Rev.0.7
BUG=b:228907558
TEST=local build and tested with Goodix touch screen
Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is
used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from
PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK.
BUG=b:229345416
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot and verify if the buzzer beeps.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG.
BUG=b:220241277
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icc8fbef1467605505459fce264697f670591c81e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Followed the Brya series to lock the gpio pins in baseboard. Variant
should honor locked gpios from baseboard, but not the last. Variant can
add more gpios to lock if needed.
BUG=b:216671701
TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that
nivviks boots successfully to kernel.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
