SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Return to empty stack before making the switch.
Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
This enables adding the backlight driver to boards that may or may not
come with a keyboard backlight function.
It's the responsibility of the EC to report if that feature exists, but
that's not a big extra burden given that it already keeps track of
everything else related to the backlight.
BUG=b:64705535
BRANCH=none
CQ-DEPEND=CL:620595
TEST=configured KBLE manually and noticed the presence/absence of
/sys/devices/platform/GOOG0002:00/ on a Chrome OS Linux kernel,
corresponding to the value reported by the EC.
Change-Id: Idc36bfaa6e69581ba19b52d37af6956f63cfdb8f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.
This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.
So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.
BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.
Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kahlee has an ambient light sensor connected to the EC.
TEST=Can see the device in /sys/bus/iio
BUG=b:62030268
Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.
BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.
Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In case there is no mode selected, sys and cpu variables are not
initialized, causing a segfault on exit (goto done).
Change-Id: I4a183c267e306598627c1612f4633f1e19019f3c
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21026
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Passing a string containing output from strerror() to perror() causes
double error message display. It is also causing segfaults when the
error message is longer than temp_string capacity.
To fix the problems, sterror() call has been removed so the error
message is printed only once. This could be enough to avoid segfaults,
but it is a good practice to limit output size with snprintf().
Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To correct the SGX init sequence; PRMRR on all cores first
needs to be set, then follow the SGX init sequence. This
patch would refactor the common SGX code (and add needed
checks in the init sequence) so that SOC specific code can
call SGX init in correct order.
Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Early serial for W83627[HF|EHG] superios are handled by
superio/winbond/common/early_serial.c. Remove code
thus deprecated.
Build tested on select affected mainboards.
Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.
[1] https://review.coreboot.org/20988
Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested:
- i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2
- debug output from serial port, EHCI debug port not found
- Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload
- all PCI and PCI Express slots
Issues:
- sometimes the machine fails to boot, with serial debug output it can
be seen it stucks after SMM initialization, and more likely to fail
to boot when serial cable is attached
- no S3 resume (not tested in vendor firmware)
Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add two additional LED IDs.
Add Kconfig menu entries to allow selecting the action
to execute on death.
Overwrite weak die_notify method to notify user on death.
Flash all LEDs and play beep code 10 depending on Kconfig
options.
Successfully tested on:
Tested on Lenovo T500.
Tested on Lenovo X200.
Tested on Lenovo T430, but only LEDs are flashing.
Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8
Signed-off-by: Patrick Rudolph <siro@das-labor.org
Reviewed-on: https://review.coreboot.org/19695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Get microcode patch pointer from intel_mp_current_microcode() api
of mp_init and change sgx_configure function signature to drop
microcode_patch param.
Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21009
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present
in the common gpio code.
Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add mp_current_microcode() function to get the microcode patch pointer.
Use this function to avoid reading the microcode patch from the boot
media. init_cpus() would initialize microcode_patch global variable to
point to microcode patch in boot media and this function can be used
to access the pointer.
Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP might have done some settings for us there. Use pci_update_config32()
since the register is documented to be 32 bits wide.
Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relevant changes (commit 2e8761e):
* Add an option to truncate the ME image file
* Add full support for Skylake (ME 11) and following, including
modules removal, truncation informations and partition
relocation
* Add two options to generate a shrinked ME image file and the
corresponding descriptor with a modified flash layout
* Update README.md
* Bug fixes
Also add a link to the usage guide in the Kconfig help.
Change-Id: I690c5d558139f64f38babf3c0988b53834ba8b37
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/20915
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clear LAST_BYTE flag at beginning of block commands.
For reads, slave device determines in the message format how
many bytes it has to transfer out, host firmware only dictates
the maximum buffer length. Return SMBUS_ERROR if only
partial message was received.
For writes, return SMBUS_ERROR if length > 32.
For writes, fix off-by-one error reading memory one
byte past the buffer end.
Change-Id: If9e5d24255a0a03039b52d2863bc278d0eefc311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A small typo in the dll setting code prevented this combination from
booting.
TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2
Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On this device libgfxinit successfully initializes textmode and
framebuffer mode on the device connected to the HDMI1 port.
VGA port is not tested, due to lack of VGA with valid EDID.
Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1.
Due to limitations within the libgfxinit's current build system,
it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is
PCH instead of CPU for which libgfxinit should be configured here.
Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fail at build-time if one of the following happens:
Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.
Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.
Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.
BUG=b:64811381
Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Kyösti Mälkki