Commit graph

2667 commits

Author SHA1 Message Date
Kyösti Mälkki
66b5e1b32d ACPI: Use common code for MADT LAPIC NMIs
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.

Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-25 15:01:49 +00:00
Martin Roth
8180427a16 soc/amd: Define post codes
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.

picasso/romstage.c did get a couple of post codes removed to match the
other files.

The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.

Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-24 15:16:45 +00:00
Felix Held
75873dbf27 soc/amd/*/fsp_m_params: rework local USB PHY table update
Update the fields that need to be updated directly in the local static
usb_phy_config struct instead of dereferencing the pointer written to
the corresponding UPD field. This will allow updating the type of UPD
field in a follow-up commit to enable 64 bit coreboot builds.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23 19:44:03 +00:00
Felix Held
3b89c95906 soc/amd/*/Makefile: fix readelf parameters to get bootblock size
This ports forward part of commit df09680626 ("soc/amd/picasso: Add
support for 64bit builds") to the newer AMD SoCs.

Use -Wl instead of -l to get the output format that the commands in the
Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this
change, readelf will split the output into two lines in case of a 64 bit
coreboot build. This results in invalid amdcompress and amdfwtool
command lines which will cause the amdfwtool call to fail with

Error: BIOS binary destination and uncompressed size are required

With the old readelf -l command we get this output in a 64 bit build:

Program Headers:
  Type           Offset             VirtAddr           PhysAddr
                 FileSiz            MemSiz              Flags  Align
  LOAD           0x0000000000000080 0x0000000002030000 0x0000000002030000
                 0x0000000000010000 0x0000000000010000  RWE    0x10

while we get the correct output in a 32 bit build:

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  LOAD           0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20

With readelf -Wl we also get the expected output in a 64 bit build:

Program Headers:
  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  LOAD           0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10

TEST=This fixes the 64 bit build on Cezanne with some follow-up patches
applied.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-23 19:43:46 +00:00
Karthikeyan Ramasubramanian
4763a5a470 soc/amd/mendocino: Increase CBFS_MCACHE size
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.

BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.

Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-21 19:56:34 +00:00
Elyes Haouas
799c321914 cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.

Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-11-18 16:00:45 +00:00
EricKY Cheng
9cbbba68b6 soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.

BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-11-18 15:54:49 +00:00
Kyösti Mälkki
2e65e9cb69 soc/amd: Use ioapic helper functions
Calling setup_ioapic() was only correct for the
IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs.

Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-17 23:31:59 +00:00
Elyes Haouas
a31ef8c242 soc/amd/common/pi/def_callouts.c: Fix log messages
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.

Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-17 13:23:09 +00:00
Fred Reitberger
2dceb126d5 soc/amd/morgana/Kconfig: Remove TODO after review
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16 19:59:06 +00:00
Martin Roth
c420d538ee soc/amd/common: Don't set gcc specific options for clang builds
Clang doesn't understand the -Wstack-usage=40960 option.  Replace it
with -Wframe-larger-than=40960.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-16 14:22:22 +00:00
Arthur Heymans
df09680626 soc/amd/picasso: Add support for 64bit builds
Tested on google/vilboz (running the PCI rom with yabel).

Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-16 04:22:00 +00:00
Felix Held
cf92ecf6f1 soc/amd: commonize generation of the PIC/APIC mapping tables
Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.

BUG=b:182782749

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15 14:29:33 +00:00
Arthur Heymans
17e68572ca soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion
Explicitly cast integers to fix building for long mode.

Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-14 22:40:02 +00:00
Felix Held
2e81436be8 soc/amd/*/root_complex: use FSP HOB iterator functions
Use the newly added functions to iterate over the FSP HOBs to report the
resources used by FSP to the resource allocator instead of open coding
the iteration over the HOBs in the SoC code.

TEST=Patch doesn't change reported resources on Mandolin

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-14 18:50:45 +00:00
Arthur Heymans
6e85740236 arch/x86/Kconfig: Move AMD stages arch to common code
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE
needs to be build as x86 stage.

Change-Id: I126801a1f6f523435935bb300f3e2807db347f63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-14 15:54:02 +00:00
Matt DeVillier
c3583173ec soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage
for PCIe reset (currently set in bootblock) and touchscreen power
sequencing (not yet implemented, but will be later in the patch train).

Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13 15:37:46 +00:00
Elyes Haouas
898176a24c treewide: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity
Change-Id: I2a255cdcbcd38406f008a26fc0ed68d532e7a721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-12 18:00:16 +00:00
Felix Held
dafc6194a0 soc/amd/root_complex: don't skip reporting IOAPIC resource in !hob case
When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-11 17:45:18 +00:00
Elyes Haouas
aba1c945cd /: Remove "ERROR: "/"WARNING: " prefixes from log messages
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.

Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-10 21:31:18 +00:00
Felix Held
753827ef33 soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.

TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:31 +00:00
Felix Held
d92bb3c3f1 soc/amd/picasso/acpi: rename pcie.asl to pci_int_defs.asl
This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2022-11-09 15:47:04 +00:00
Karthikeyan Ramasubramanian
5717ce6e99 soc/amd/common/block/spi: Mainboard to override SPI Read Mode
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.

BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
  11:start of bootblock                                688,046
  14:finished loading romstage                         30,865
  16:FSP-M finished LZMA decompress (ignore for x86)   91,049
Total Time: 1,972,625

After:
  11:start of bootblock                                667,642
  14:finished loading romstage                         29,798
  16:FSP-M finished LZMA decompress (ignore for x86)   87,743
Total Time: 1,943,924

Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-11-09 13:40:02 +00:00
Jakub Czapiga
605f793af8 vboot: Introduce handy vboot reboot functions
This patch groups vboot context, recovery reason and subcode saving, and
reboot calls into two handy functions:
- vboot_save_and_reboot() - save context and reboot
- vboot_fail_and_reboot() - store recovery reason and call function
  above

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-11-08 14:44:54 +00:00
Karthikeyan Ramasubramanian
06d5b8b7fe soc/amd/mendocino: Enable x86 SHA accelerator
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.

Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 14:57:16 +00:00
Fred Reitberger
5e8e911b7c soc/amd/common/include/gpio_defs.h: Add comment for accuracy
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other
SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times
slightly.

Time  PCO      Others
1mS   0.915mS  1.220mS
2mS   2.013mS  2.684mS

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-07 12:24:32 +00:00
Nikolai Vyssotski
b02a5014ea src/soc/amd/mendocino: Enable override of MAINBOARD_BLOBS_DIR
When using site-local we need to have ability to override
MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in
site-local). site-local Makefiles.inc should be pulled in first
(different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten.

Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-04 20:45:24 +00:00
Fred Reitberger
aab7f04904 soc/amd/*/data_fabric: Use common device ops
Use the common device ops instead of an soc-specific device ops.

TEST=builds for each soc

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:39:32 +00:00
Fred Reitberger
1a9ac34721 soc/amd/common/data_fabric: Make common device ops
Add the generic data_fabric_acpi_name function and device ops to common
code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I12053389a12081ddd81912a647bb532b31062093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:38:55 +00:00
Fred Reitberger
63c5a0d516 soc/amd/mendocino/data_fabric.c: Make function more generic
Make the data_fabric_acpi_name function more generic, in preparation to
move it to common.

TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:37:50 +00:00
Fred Reitberger
2890841e6f soc/amd/*/data_fabric: Move register offsets to soc
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.

Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:36:49 +00:00
Fred Reitberger
437d011621 soc/amd/common/block/data_fabric: Use register bitslice structs
Now that the socs have defined the DF FICAA and MMIO Control registers,
update the common code to use them.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 20:36:20 +00:00
Martin Roth
bcb610a559 soc/amd: Specify memory types supported by each chip
This change disables support for memory types not used by each of the
chips.  This will in turn remove the files for those memory types from
the platform builds.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:00:27 +00:00
Martin Roth
b6877e401a soc/amd/common: Only call into enabled memory types
Don't call into disabled memory type code, it won't work.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-04 01:00:22 +00:00
Fred Reitberger
506014f624 soc/amd/glinda/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields, updated per
glinda ppr #57254, rev 1.51

Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:49:48 +00:00
Fred Reitberger
89a987899e soc/amd/morgana/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields, updated per
morgana ppr #57396, rev 1.52

Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:49:22 +00:00
Fred Reitberger
cdac3aeb11 soc/amd/mendocino/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I01dcea783542ecc0a761191907c1273016f854c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:52 +00:00
Fred Reitberger
a9b09547d8 soc/amd/picasso/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:24 +00:00
Fred Reitberger
f5df69d1ae soc/amd/cezanne/data_fabric: Add register bitslice struct
Add structs to define the data_fabric register bitfields.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib5045812fb05eb8c3fb818d807e34decf69c6fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:48:03 +00:00
Fred Reitberger
31e6298429 soc/amd/*/data_fabric: move data_fabric_set_mmio_np to common
The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 19:47:38 +00:00
Elyes Haouas
f743e0c0e4 soc/amd: Include <cpu/cpu.h> instead of <arch/cpu.h>
Also sort includes.

Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-03 13:07:39 +00:00
Martin Roth
9231f0b92a soc: Add SPDX license headers to Makefiles
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-31 03:27:13 +00:00
Martin Roth
222f1272ba soc/amd/common: Initialize STB Spill-to-DRAM
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I547671d2bcfe011566466665b14e151b8ec05430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29 22:50:26 +00:00
Felix Held
396fb3db74 soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device
Don't set bit 2 in _STA in order for Windows not to show a warning about
an unknown device in the device manager for this device. Since the _STA
object just returns a constant, a name definition can be used instead of
a method definition.

TEST=The unknown device with device instance path ACPI\AAHB0000\0
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.

Just shutting down and then booting it again won't clear some internal
state in Windows, so a reboot is needed instead for the change to become
visible.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-29 22:49:33 +00:00
Martin Roth
9b6018c4a6 soc/amd/glinda: Don't add amdfw.rom to cbfs in SOC Makefile
CB:66943 - commit 8d66fb1a70 (soc/amd: Add amdfw.rom in coreboot.pre)
changed the build flow for the amd firmware binary after glinda was
branched from morgana.  Update glinda to match the other SoCs.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-29 02:38:34 +00:00
Martin Roth
530b111c42 soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:37:24 +00:00
Martin Roth
300338fccf soc/amd/mendocino: Add code for printing STB to boot log
This adds the mendocino specific code for printing the STB data to the
boot log.  It still needs to be enabled in the mainboard to be used.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:36:22 +00:00
Martin Roth
7e3c1ced40 soc/amd/common: Add code to print AMD STB to boot log
This allows platforms that support AMD's STB (Smart Trace Buffer) to
print the buffer at various points in the boot process.

The STB is roughly a hardware assisted postcode that captures the
time stamp of when the postcode was added to the buffer.  Reading
from the STB clears the data.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-28 21:36:02 +00:00
EricKY Cheng
f7a09278b6 soc/amd/mendocino: Expand extra 5 DPTC thermal related profiles
Expand extra 5 DPTC thermal related profiles for
Dynamic Thermal Table Switching support.

BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie03de155325cbb340fce09848327ff7fa33ab1fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-28 21:30:54 +00:00
Fred Reitberger
f78e844b55 soc/amd/cezanne/Kconfig: Enable APOB_HASH
Enable the APOB_HASH feature. This improves boot times by ~9.5ms.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9261d101eb23465208affbf815385d3f1bdbcd69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-28 19:56:58 +00:00