Commit Graph

19185 Commits

Author SHA1 Message Date
Duncan Laurie 6733e7d54f chromeec: Update Chrome EC submodule
Update to Chromium TOT with ea1a8699e96425806abdd532d04da254ae093f6e

Change-Id: I28b9f415a4d55442c294abd27c344a91608a06c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-29 01:24:47 +02:00
Furquan Shaikh 566feddece soc/intel/common: Add reset.c to postcar
ramstage_cache_invalid which was added in
I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112)
requires hard_reset to be defined in postcar stage.

BUG=None
BRANCH=None
TEST=Compiles successfully for reef.

Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-29 00:23:09 +02:00
Furquan Shaikh 4ef7491b22 Documentation: Add documentation for GPIO toggling in ACPI AML
This document provides information about the different functions that a
driver can use for generating ACPI code for toggling GPIO. These
functions are expected to be implemented by the SoC. It also defines the
different constraints on use of Local variables in ACPI code while
implementing these functions.

BUG=chrome-os-partner:55988

Change-Id: Ibc03d766afb6d7b75bc0dc9f79920b561f1c4a78
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-29 00:13:06 +02:00
Elyes HAOUAS a299345f4a nb/intel/i945/gma.c: Homogenize code for PCI IDs.
Change-Id: Ic01565cb730c49a5fe77c8f4990276970964f101
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17174
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-29 00:00:43 +02:00
Ronald G. Minnich 66bea528cf riscv: add the lowrisc/nexys4ddr mainboard
This was tested at the coreboot meeting in Berlin.

The uart programming may still not be right but when used with
the lowrisc bitstream for the board we were able to load
and start linux, although it does not yet get far due to
PTE version issues with lowrisc.

Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17132
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-28 21:09:06 +02:00
Sumeet Pawnikar aa75cdc1b2 lars/kunimitsu: Add other sensor in _ART for fan control
This patch updates the _ART table with other external sensor
TSR0 for Fan speed control on Skylake-U based Kunimitsu and
Lars boards.
Also, updates the temperature values in DPTF policy for
better performance.

BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified this updated _ART table on these boards with
different workloads.

Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332349
Reviewed-on: https://review.coreboot.org/17066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-28 20:16:52 +02:00
Paul Menzel a3a6746495 Makefile.inc: Explicitly disable PIE
Some distribution compilers enable Position Independent Executable (PIE)
by default, causing a build failure.

So explicitly disable PIE by passing the flag `-fno-pie`, to fix the
build error.

Change-Id: I1b7d7168e34c5c93c25bc03ffa49b2eeac0e76f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/17097
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-28 20:16:33 +02:00
Paul Menzel 246051c22c util/xcompile/xcompile: Add a space before `&&`
Change-Id: I07fd4d6f6db220e23da8daced6014ce39894c604
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17159
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-28 20:16:13 +02:00
Aaron Durbin 083e2e4ec4 mainboard/google/reef: allow variants to override NHLT OEM strings
In certain cases a board variant may need to override the NHLT
OEM strings in the main NHLT table. Therefore, provide that path.

BUG=chrome-os-partner:56918

Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17167
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2016-10-28 19:02:35 +02:00
Aaron Durbin 558c8a57b9 mainboard/google/reef: update comment for DMIC config usage
Going forward GPIO_17 is used to determine the configuration of
the board w.r.t. the number of DMICs on the board.

BUG=chrome-os-partner:56918

Change-Id: I03edb880e0649977030c1b87219ebebac631a519
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17163
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-28 19:02:11 +02:00
Aaron Durbin 64606cea93 soc/intel/skylake: don't hardcode GPE0 standard reg
While using '3' is fine for the standard gpe0 for skylake, I want
to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX
without the hard coded index. If that does happen now things will
still work, but it may just not match the hardware proper.

BUG=chrome-os-partner:58666

Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-28 19:01:48 +02:00
Duncan Laurie 11afdbf67c chromeec: Update submodule
Update the chromeec submodule to current Chromium TOT.

Change-Id: Ia3d913703fdea0ece02074d8e2d4b30d97e9a97c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28 18:59:55 +02:00
Duncan Laurie c806e4cc59 skylake: Add GPIO macro for configuring inverted APIC input
Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted.  This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.

BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS

Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28 18:59:46 +02:00
Aaron Durbin ffddf7beb4 soc/intel/skylake: put back uart_debug.c into verstage
uart_debug.c was accidentally dropped in verstage in
64ce1d122c
(https://review.coreboot.org/17136). Fix that.

Change-Id: If37a028550d419bada80d157c4de02fd82d26c89
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17175
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-10-28 17:04:31 +02:00
Kyösti Mälkki e1c36aecd8 pcengines/apu1: Add RS485 configuration
In RS485 mode RTS line acts as a transceiver direction control.

The datasheet is not very clear about the polarity but register setting
here is tested to drive nRTS line high when transmitting.

Also note revision of B of the super-IO has errata and 8N1 setting does
not work properly, you would need revision C of the chip assembled to
fix this.

Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14998
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-10-28 16:56:55 +02:00
Martin Roth 78f73353a3 util/lint/lint: Show lint script output as it's running
The checkpatch script takes a really long time to run, and when the
output is buffered to wait until it's finished, it's hard to tell if
the script is actually doing anything.

Instead, use tee to log the output and display it at the same time.

Change-Id: I3cf36e5e6ca28584103888ee1c6f125320ac068a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17125
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-10-27 22:20:22 +02:00
Arthur Heymans 46dd467648 Do not select SEABIOS_VGA_COREBOOT by default when building for QEMU
On QEMU using SeaVGABIOS breaks some bootloaders, e.g. ISOLINUX does not
work and GRUB works but is forced in txtmode, instead of graphical mode.

Change-Id: If31d4e5ed19cbeed3f8f9dbc23cc738dd55986e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17122
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27 18:52:30 +02:00
Naresh G Solanki 38f5a577ca soc/intel/skylake: make inline function static
Make bootblock_fsp_temp_ram_init as static inline.

Change-Id: Iacf24728a45fc6554d7a425feecc25e55ac5da6c
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17084
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-27 17:01:56 +02:00
Naresh G Solanki d5353e3648 driver/intel/fsp2_0: Reset on invalid stage cache.
Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is
invalid during S3 resume.

Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 17:01:46 +02:00
Aaron Durbin 6ea1500e48 mainboard/google/reef: drop disabling periodic training for micron
In anticipation of getting fixed material remove the disabling of
periodic training for MT53B512M32D2NP and MT53B256M32D1NP.

BUG=chrome-os-partner:59003

Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17130
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27 16:52:01 +02:00
Aaron Durbin ed5b8bf3ed mainboard/google/reef: clarify memory part number details
Explain the reasoning for the part_num strings used in the
memory SKU table explaining the necessity of keeping mosys
in sync with the strings used. It's possible that actual part
numbers could change as the higher speed material gets cheaper,
for example.

BUG=chrome-os-partner:58966

Change-Id: If895e52791dc56e283261b3438106116b8b2ea05
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17129
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 16:51:50 +02:00
Duncan Laurie 8d01902bb7 skylake: Add support for eSPI SMI events
Add the necessary infrastructure to support eSPI SMI events,
and a mainboard handler to pass control to the EC.

BUG=chrome-os-partner:58666
TEST=tested on eve board with eSPI enabled, verified that lid
close event from the EC during firmware will result in an SMI
and shut down the system.

Change-Id: I6367e233e070a8fca053a7bdd2534c0578d15d12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17134
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 16:30:54 +02:00
Duncan Laurie f0ba2259b8 skylake: Prepare GPE for use in bootblock
Export the pmc_gpe_init() function from pmc.c to pmutil.c
so it can be used in bootblock, and then call it from there
to initialize any GPEs for use in firmware.

BUG=chrome-os-partner:58666
TEST=test working GPE as TPM interrupt on skylake board

Change-Id: I6b4f7d0aa689db42dc455075f84ab5694e8c9661
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17135
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27 16:30:36 +02:00
Duncan Laurie 64ce1d122c skylake: Support for early I2C TPM driver
Add the SOC definition for acpi_get_gpe() so it can be used
by the I2C TPM driver.  Also add the I2C support code to
verstage so it can get used by vboot.

BUG=chrome-os-partner:58666
TEST=boot with I2C TPM on skylake board

Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17136
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 16:30:13 +02:00
Duncan Laurie 95f9020de1 skylake: Fix wake source reporting with Deep S3
The Deep S3 state will lose a lot of register contents that we
used to rely on for determining wake source.

In order to make use of this override the enable bit for wake
sources that are enabled for Deep S3 in devicetree.cb.

BUG=chrome-os-partner:58666
TEST=check for _SWS reporting wake source on S3 resume on skylake

Change-Id: If5113d6890f6cbecc32f92af67a29952266fe0ac
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17137
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 16:30:01 +02:00
Duncan Laurie 135c2c4817 skylake: Use COMMON_FADT
Remove the FADT from the individual mainboards and select and
use COMMON_FADT in the SOC instead.  Set the ACPI revision to 5.

Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17138
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27 16:29:53 +02:00
Kevin Paul Herbert 0d2bb80a86 FILO: update STABLE
The STABLE build of FILO does not build anymore with the
current HEAD of coreboot. However, the current HEAD of FILO
does build with the current HEAD of coreboot. Update FILO
STABLE to FILO HEAD.

Change-Id: I4eece3aaada0dfdf4da106d5d260b5b361537558
Signed-off-by: Kevin Paul Herbert <kph@platinasystems.com>
Reviewed-on: https://review.coreboot.org/15195
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-27 16:18:38 +02:00
Kyösti Mälkki 3e71dc591b payload choice: Fix build of FILO
Actual build was missing libpayload path.

Change-Id: I519869d2d64c66b3d1d557595c7d13c22cd40819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17114
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-27 16:17:13 +02:00
Furquan Shaikh 8be4fdfcc1 google/reef/variants/pyro: Use WCOM Touchscreen driver
BUG=chrome-os-partner:57846

Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-26 22:52:07 +02:00
Furquan Shaikh 16e660560a drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
BUG=chrome-os-partner:57846

Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17092
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-26 22:51:57 +02:00
Arthur Heymans f8a4f41d48 nb/x4x/gma.c: Remove writes to DP, FDI registers
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.

Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17111
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26 22:39:35 +02:00
Arthur Heymans 606b8bccb5 nb/gm45/gma.c: Remove writes to DP, FDI registers
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.

Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-26 22:38:43 +02:00
Nico Huber 04be6b5949 nb/intel/i945: Add PCI id for I945GC
Also drop an odd comment about the resource allocator which seems to
work fine, with the right id.

Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17095
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26 22:37:52 +02:00
Furquan Shaikh 3bfe3404df intel/skylake: Add support to enable wake-on-usb attach/detach
Three things are required to enable wake-on-usb:
1. 5V to USB ports should be enabled in S3.
2. ASL file needs to have appropriate wake bit set.
3. XHCI controller should have the wake on attach/detach bit set for the
corresponding port in PORTSCN register.

Only part missing was #3.

This CL adds support to allow mainboard to define a bitmap in
devicetree corresponding to the ports that it wants to enable
wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
PORTSCN would be set by xhci.asl for the appropriate ports.

BUG=chrome-os-partner:58734
BRANCH=None
TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
attach/detach.

Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-26 08:33:37 +02:00
Furquan Shaikh ffb3a2d225 soc/intel/apollolake: Enable write-protect SPI flash range support
Use intel common infrastructure to enable support for write-protecting
SPI flash range. Also, enable this protection for RW_MRC_CACHE.

BUG=chrome-os-partner:58896
TEST=Verified that write to RW_MRC_CACHE fails in OS using
"flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"

Change-Id: I35df12bc295d141e314ec2cb092d904842432394
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17117
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-26 01:51:00 +02:00
Furquan Shaikh 723a84e292 soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896

Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17116
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26 01:50:45 +02:00
Furquan Shaikh aedbfc8f09 soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.

BUG=chrome-os-partner:58896

Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-26 01:50:36 +02:00
Ronald G. Minnich 5817a15557 riscv: add the lowrisc System On Chip support
Change-Id: I8d81b9cf280e724c935106c8f00692300094ad3f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17119
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-25 22:31:06 +02:00
Arthur Heymans 64e341ec16 mb/ga-g41m-es2l: remove unneeded IGD IRQ setting in ACPI
According to: "Intel ® 4 Series Chipset Family datasheet"
the IGD only has 1 IRQ pin.

Change-Id: I974f002f5a213056f4593a1eab10772527bb241d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17098
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25 21:23:06 +02:00
Arthur Heymans c057a0611b nb/i945/gma.c: Set the MSAC register correctly
This fixes an instability on 945gc where the IGD completely locks
up the system, when for instance tasked to do something with
compositing (like GNOME or GDM).

TESTED on ga-945gcm-s2l and d945gclf
TEST: launch GDM (gnome display manager)

Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17094
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2016-10-25 21:22:16 +02:00
Naresh G Solanki ab5d6902fd mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3
Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.

Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.

* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.

This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.

Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 21:20:06 +02:00
Martin Roth 9369e10f1f payloads/external/Makefile.inc: Clean up makefile
- Add comments dividing the payload sections.
- Move separate TINT and Memtest sections that were intermingled.

Change-Id: If0bbd6e182359c5186a8b958dd2c9ab9f0e0a3f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17046
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25 21:14:36 +02:00
Aaron Durbin 06590a2014 Revert "soc/apollolake: Add soc core init"
This reverts commit a52f883b10
(https://review.coreboot.org/16587).

The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.

BUG=chrome-os-partner:58994

Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-10-25 19:27:50 +02:00
Yidi Lin 79daac9890 google/oak: Add derivative board Hana
CQ-DEPEND=CL:379684
BUG=chrome-os-partner:58064
TEST=verified on hana rev0

Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8
Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/379504
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:10:49 +02:00
Patrick Georgi 4003283c51 util/scripts: add copyright notices
Change-Id: Ia40543e5585845e5e6c178a620052c6a25927a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:10:14 +02:00
Lin Huang 4ef9899bfe rockchip/rk3399: gru/kevin: drop unused sdram configs
There are some sdram configurations that are no longer used. Drop them.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c
Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/399122
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17103
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:09:55 +02:00
Patrick Georgi cd48d19836 Rename and move util/gitconfig/rebase.sh
It has nothing to do with git configuration, but is one of our
convenience scripts. It also has nothing to do with rebases (except that
it can be comfortably used through git rebase --exec)

Change-Id: Icc60c4de486a0027fe2230e93b441e62ba022193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17101
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:09:19 +02:00
Patrick Georgi 45037c8732 Drop convert-all-depthcharge-fmap.dts.sh script
The relevant data is gone in Chrome OS depthcharge's master branch, and
so the script outlived its usefulness.

Change-Id: I04f3f168e23d4bc7c31692263a8eec3f97ee50de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/17100
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-25 17:09:12 +02:00
Lin Huang df3321aa34 rockchip/rk3399: reset system if DDR init fails
We found sdram may fail in pctl_cfg(), so we check the status in this
function. If it exceeds 100ms still in this function, we will restart
the system. We also found there are rare chances DDR training fails,
so also restart system in that case.

BUG=chrome-os-partner:57988
BRANCH=None
TEST=coreboot resets on failure and eventually the system comes up

Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11
Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/397439
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17045
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25 17:08:58 +02:00
Jonathan Neuschäfer 65a9462a73 mb/emulation: Select QEMU-i440fx by default
It's a better default than QEMU-armv7, which is currently the default
board when coreboot is configured for the first time, because most
coreboot development targets x86.

With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU
become:

    git clone https://review.coreboot.org/coreboot.git && cd coreboot
    make crossgcc-x86
    make olddefconfig && make
    qemu-system-x86_64 -bios build/coreboot.rom

Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-25 01:31:43 +02:00