This patch is to change method of HID assignment with compatible id
style in nau8315_config and allow mainboards to set it.
Signed-off-by: David Lin <CTLIN0@nuvoton.com>
Change-Id: Ia6f02e495eeb06290947edc9e44fa25a4ce18956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69965
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Enable wifi sar function for yaviks.
Use the fw_config to separate SAR setting for different wifi card.
BUG=259199095
TEST=build, enabled iwlwifi debug, and check dmesg
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Update SX9324 RegProxCtrl0 register settings based on tunning value
from P-sensor vendor.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28 on Pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Remove the `const` property from chip_get_common_soc_structure so that
the returned values can be overwritten as required.
Cc: th3fanbus@gmail.com
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7d3db0bc119cd9b9b276abd68754e750e06a788c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase the default linear framebuffer max height/width for desktops
so that native display resolution works properly on 2160p and 1440p
ultrawide displays.
TEST=build/boot google/fizz, verify libgfxinit display init works
properly on 3440x1440p and 3840x2160p displays.
Change-Id: I95a1f1275a4faea195b73997c648023119807958
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Unlike gcc, a clang build will fail when only a comment is used to
indicate that the fallthough is intended. To fix the clang build, use
__fallthrough instead. This will fix the build errors introduced by
commit f45c7671d9 ("Set x86_64 as supported architecture for clang")
that enabled clang builds for a case that uses yabel to run the VBIOS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ed337025adeb833f352d198fc0f13b5e1c209c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70889
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The original value of the `DevIntConfigPtr` is unknown, and there's no
way to be absolutely certain that it actually points to usable memory.
Instead of copying the data, update the pointer's address to reference
the global variable directly. It is assumed that FSP does not write to
the memory pointed by `DevIntConfigPtr`. Confirming this assumption is
pointless; one might as well reimplement FSP instead.
Change-Id: I90594cc09e3fa2aef98658441c323a44a869635b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65217
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL
FSP headers for lisbon.
BUG=b:246657849
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=lisbon emerge-brask intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
flash and boot lisbon to kernel.
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
dw_i2c_transfer returns an enum cb_err type, but dw_i2c_dev_transfer
returns an int, so explicitly translate between the types. Since
dw_i2c_transfer only returns either CB_SUCCESS or CB_ERR which are
defined as 0 and -1, this won't change behavior of dw_i2c_dev_transfer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2cbcf6564035d5c0fc13f5d5e7ac0d0425e85d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This configuration also boots on real hardware.
Change-Id: Ic62a33f8d8c3fdaa8182e797b2bf6fbed6b55731
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This boots on both qemu and real hardware now.
Change-Id: Ibd320059cff575847bbf1844b5bb100312f77916
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Clang generates R_X86_64_32S symbols that get truncated.
TESTED:
- prodrive/hermes boots with GCC and clang
- MTRR are properly cleared (tested by filling in both
MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing)
Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement some scaffolding for Haswell native raminit, like bootmode
selection, handling of MRC cache and CPU detection.
Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement native thermal initialisation for Lynx Point. This is only
needed when MRC.bin is not used.
Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64180
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement native USB initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement native early ME init for Lynx Point. This is only needed when
MRC.bin is not used.
Change-Id: If416e2078f139f26b4742c564b70e018725bf003
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.
TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable unused PCIE8 for fix system can not enter S0ix completely.
BUG=b:261915226
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename the MIPI PWM control GPIO to be consistent with the schematic.
BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB
Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There are two ways to control backlight in geralt:
1. MIPI/eDP panel => control backlight via the GPIOs.
(`backlight chip enable` and `PWM dimming control`)
2. eDP OLED panel => enable backlight via `backlight chip enable` and
control dimming over AUX.
For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs
will be passed from coreboot. For eDP OLED panel(#2), only the
"backlight enable" GPIO will be passed. If depthcharge successfully gets
the GPIOs, it will use them to control backlight.
BUG=b:244208960
TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB
Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct touchscreen setting to make touchscreen function workable.
BUG=b:260565911
BRANCH=firmware-brya-14505.B
TEST=Built and verified touchscreen function
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
dw_i2c_soc_dev_to_bus will return -1 if it failed to find an I2C bus
number for a device. In this case return -1 instead of implicitly
casting the -1 to an unsigned int and passing that as bus number to
dw_i2c_transfer. The dw_i2c_base_address call inside _dw_i2c_transfer
already ended up handling this error case correctly, but better handle
the error more directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06b6005cee0c5c43855cb5b388a9911fc286c984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There's no need to call die() in the case that the MMIO address of the
I2C controller is NULL, so handle this case by returning a failure
instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12c143916ad551c56cc4ff75ae23754018817505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This fixes the following error:
In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21:
src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment]
PXEN, 1, /* Enable */
^
Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
If the temporary nvdata storage inside the vboot context is already
initialized then return immediately without reinitializing from the
backup NV storage. This allows vbnv_init to be called more than once.
Also the check to enable USB Device Controller (UDC) happens after
NVdata is initialized. Hence the nvdata in vboot context can be used
instead of reading from the backup storage again.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.
Change-Id: Id72709e2fc3fe6a12ee96df8df25e55cf11e50a7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
After the previous patch this local variable is no longer the mpinit CPU
index, but the LAPIC ID, so rename it. Since it will only be set once,
it can also be marked as const.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fad4e1095478213727bee8586852f9d5a7d18e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70798
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This patch updates the GPIO PIN name as per Proto 1 schematics dated
12/14/2022.
TEST=Not code change, just updated the comment section.
Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This was done previously for ADL. moving the code to common so
it can be leveraged for other platforms (e.g. MTL)
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex
instead of spd-9.hex.
Reserve RAM ID 3 for it, so the RAM ID table remains the same.
BUG=b:261530632
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage
Then boot devices successfully
Change-Id: I1b683168310f74a07d246af8618b977cce32287a
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD.
Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E.
BUG=b:261530632
BRANCH=None
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff
minimum 500ms requirement.
BUG=b:260380268
TEST=Build and boot on pujjo
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
BUG=none
TEST=Build and boot to the OS on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 148e5b83:
Makefile: Fix and simplify the RUNTEST test wrapper
to commit id 196b0843:
create_new_keys: use single AP RO Verification root key pair
This brings in 30 new commits.
Change-Id: Iedfc6cf0ff2dc1913a7a41a4302dc1951abf8a8a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings
Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The cpu_index function can't be used before mpinit, so use lapicid calls
instead. This fixes the regression introduced by commit 4c3749884d
("cpu/x86/mtrr: Print cpu index number when set up MTRRs for BSP/APs")
and also reverts also commit b3261661c7 ("cpu/x86/mtrr/mtrr: fix
printk format strings"), since lapicid returns an unsigned int while
cpu_index returns an unsigned long.
TEST=Mandolin boots again and doesn't fail when it first tries to print
the MTRR configuration
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0d226704051ab171891775a618ce7897b74fde16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70797
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The calculation for mem_chip_info_total_density_bytes() may already
overflow in the intermediate 32-bit calculations before being assigned
to the 64-bit result variable. Fix that.
Fixes Coverity issue: CID 1501510
BRANCH=corsola
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I73da014c953381974c6ede2b17586b68675bde2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add PCIe RTD3 support for Skyrim
BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times
Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
David Lin