The codec interrupt needs to be active high because multiple
interrupt sources share this line:
1) Headphone plug detect
2) Mic present
3) Hotword detect
These interrupt sources are OR-ed together.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=Jack detection works on samus
Change-Id: If35fe8493ab30d878d9fac2251acee62c776b0eb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 348608fe61f7848db2bfd22502a0c259d24f8980
Original-Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220588
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9268
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GPIO IRQ support has been added in upstream rt5677 driver,
with new jack detect platform config options.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=headphone and mic detect works on Samus
Change-Id: I68a675ccd1fec3e5329d57aadad3229053092026
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4b90fa2f557f603661e25c9e1b4712eea15c8502
Original-Change-Id: I379087b8acdb13e65776a18c9ee3a58d4cb4e73c
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224513
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9266
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This matches the label exported by the GPIO controller in the
kernel and allows more speicific matches if there are other
devices that also export GPIOs.
BUG=chrome-os-partner:33098
BRANCH=samus
TEST=crossystem wpsw_cur returns 1
Change-Id: I96f8d0f7f9fd584be4a6f14d13e04db0a88951a8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 736679136a0a72874304eaeae1ac58633cd2ce14
Original-Change-Id: I655549d0f0eca341581bfbf845162d8b9f5e993d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224136
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since the PD software sync is slow enable support for displaying
a screen telling the user that something is happening.
BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.
Change-Id: Ib6c4cc03952768ece76832efc84f665c52191ffb
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 6971d74ff50ced0ef94d5fec26c0e6a071d207b2
Original-Change-Id: I125744f58c6b84df1af3943d9be98fe55c7117d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223850
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9264
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of having this in mosys just have coreboot report the
board version in SMBIOS tables.
BUG=chrome-os-partner:32359
BRANCH=samus
TEST=build and boot on samus, check /sys/class/dmi/id/product_version
Change-Id: I09d235752f4c870f99fb8c6a280e2bf9aba7e137
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 08413589ba84b07ff64c9116ca5fcc991cee3b89
Original-Change-Id: Ib851d2e79ed721dcbc1c2f2eda6da50cac064cf3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223096
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is the specific codec setup platform data for samus.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=emerge-samus coreboot
Change-Id: I00d4a2f73810f5f7bad49922321fb1c340289770
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 813c45bc3fdd7a2fb84df0e24bd470003bf4eafa
Original-Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221539
Original-Reviewed-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: http://review.coreboot.org/9261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The codec interrupt needs to come from codec GPIO1, so use the
HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The
This means codec interrupt is GPIO46 which is PIRQO and should be
interrupt 30.
Also add GPIO defines for the GPIOs attached to the codec itself.
These are defined by index, and I used the same "jack detect" and
"mic present" indices that were used in baytrail.
The codec interrupt to the host is added at index 2 and the
hostword detect interrupt to the host is added at index 3.
These can be changed as we work through the implementation in the
kernel driver.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: Id9cb083ddf9df161be314da4148740ed9f4d0fe6
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 3958efb28813c664a8a4219f78bdd0fcfe75c706
Original-Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220326
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9216
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Move _PRW to the ACPI devices for the touchpad and touchscreen.
Add a _DSW method, but disable it by default for now until a
spurious wake issue can be resolved.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=build and boot on samus, ensure trackpad does not
spuriously wake the system.
Change-Id: I3160248ef6dfeccdec765553643d9b8de2bb2ed1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 85d14842aefdb29c750009c0092f055587172dac
Original-Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220325
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9214
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board
BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I50f1599aa4266ed61749cc7f4229a9384b498df2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0e3ebcb8659c92874d3ca89fa3a6795c9b6eebfa
Original-Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220321
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to not break FAFT, and to have a quicker recovery
mode boot, reboot the PD controller into RO image in romstage.
This is done before the EC since rebooting the EC into RO will
also reboot the host.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
and ensure that the PD controller is rebooted to RO in romstage.
Change-Id: Ieb51717c17fdcbda7aa63b6a9404959e8736c08f
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 19237f6a338fa1c593867d8dfda1edcd376878af
Original-Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mark GPIO42 as unused according to Samus schematics
BUG=None
TEST=Make the chnage; Pass the build process; Need someone having
the board perform the verification.
Change-Id: Ib53a3ae062d414a2c98ec0756e759760d179e3fd
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4e0f8f3276c575ff60fbda709de5d3cfe31a5900
Original-Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217344
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9199
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
echo is evaluated by a shell builtin producing non-binary
spd data of the form '-e -n \<byte>'. Correct this by
using printf builtin which does the equivalent and is
more cross platform friendly.
Boards changed:
gizmosphere/gizmo
gizmosphere/gizmo2
google/bolt
google/falco
google/link
google/peppy
google/rambi
google/samus
google/slippy
pcengines/apu1
Change-Id: Iefdaf59903b9682cc88c94fd991883b560616492
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9196
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names. The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.
This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.
Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6
Reviewed-on: http://review.coreboot.org/8972
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Samus has a PD MCU, and should handle PD MCU host events.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Verify that ACPI Notify routine is called when
host event is sent from EC.
BRANCH=None.
Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214860
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg@chromium.org>
(cherry picked from commit d0752be013f66313d4218338e62372d0f5975097)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6
Reviewed-on: http://review.coreboot.org/8969
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
I was using the wrong datasheet for these parts. Revert
to the previous geometry settings so they work again.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211610
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I52ed3609c9686fef13711578597065ca4e907df4
Reviewed-on: http://review.coreboot.org/8951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f
Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Original-Reviewed-on: https://chromium-review.googlesource.com/210870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a
Reviewed-on: http://review.coreboot.org/8950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- geometry was incorrect for 8GB modules, should be x32,
so refactor the rest of the geometry to match
- some of the timing values were off, calcualte new values
from the datasheet
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210660
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1
Reviewed-on: http://review.coreboot.org/8948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This must be committed at the same time as the corresponding
depthcharge change which updates the fmap.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=Build samus firmware.
dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and
PD_MAIN_B sections.
Boot samus. 'crossystem mainfw_act' -> A
As root, 'crossystem fwb_tries=1'
Reboot samus. 'crossystem mainfw_act' -> B
CQ-DEPEND=CL:208984,CL:*169850,CL:208989
Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e
Original-Signed-off-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208899
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837
Reviewed-on: http://review.coreboot.org/8219
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
In order to ensure that we meet timing requirements for the SSD
power sequencing delay bringing the SSD out of reset until after
memory training.
BUG=chrome-os-partner:29914
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208155
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317
Reviewed-on: http://review.coreboot.org/8215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
- Turn on keyboard backlight early in boot (not resume) path
as a sign of life for the system
- Add ACPI device for keyboard backlight so the kernel can find
and make use of it
BUG=chrome-os-partner:30586
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208152
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4
Reviewed-on: http://review.coreboot.org/8213
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable the ACPI Device for the EC ALS.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d
Reviewed-on: http://review.coreboot.org/8133
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix
BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Both DDI ports may be used on this board so it needs to be
able to detect a device on either port.
BUG=chrome-os-partner:28234
TEST=None (needs hardware)
Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099
Reviewed-on: http://review.coreboot.org/8046
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Put all the SPD related information in one place including
the onboard SPD sources and the board specific parsing.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201082
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123
Reviewed-on: http://review.coreboot.org/8006
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.
samus: Move SPD handling to separate file
The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.
It relies on the updated pei_data structure from broadwell instead
of the haswell interface.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Move PEI data structure init to separate file
This needs to be executed in both romstage and ramstage
for the different PEI binary stages.
It uses the broadwell interface now instead of haswell.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Convert mainboard to use soc/intel/broadwell
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922
(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Add some code to print basic info from SPD
The handling of LPDDR is a bit messy in Intel platforms. There
is no traditional SPD so instead one is created by hand from the
provided datasheets.
These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.
This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.
Change-Id: Id3b16872f62660393d938d6f95977a4e3842d0d1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7690
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This config is used only to generate PIRQ table. If no such table is
supplied there is no need for config.
Change-Id: I537d440f53019a6bf7f190446074e75e7420545a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7566
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Change-Id: Iac53462ab3621d96ba15e2fde2800212584246db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7072
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Move NFC_INT to GPIO9
Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42
Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43
Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L
Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6)
samus: Misc fixes from proto1b bringup
- NFC interrupt is expected in the kernel as a GPIO now,
so set it back to that type
- NFC FW update GPIO should be low
- Accel/Codec interrupts were still set as GPIO type,
they should be set as PIRQ type
Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176513
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688)
Squashed two small patches for samus.
Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6852
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- GPIO29 is no longer connected so we don't need the SMI workaround
on the entry to sleep states.
- Disable touchscreen wake source until the kernel driver is working
so it does not wake immediately.
- Update a few GPIOs and disable the codec for now as it is leaking
into the 1.8V DDR rail.
Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174122
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The LPDDR3 memory is x32 and dual rank with 14 row bits.
In addition the memory is actually elpida, even though
they are owned by micron it is confusing to label it as such.
And the ram strap options were inverted from what I expected
so the memory table needs to be updated.
Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6828
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
