Add sdram_configs.c to both romstage and ramstage.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=Build ok on Foster
Signed-off-by: Yen Lin <yelin@nvidi.com>
Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1
Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb
Original-Reviewed-on: https://chromium-review.googlesource.com/280290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
Reviewed-on: http://review.coreboot.org/10951
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
get_sdram_config() (in sdram_configs.c) will be needed in ramstage.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=Build ok on Smaug
Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed
Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277373
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10950
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is a result of the Silcon Observation. On warm reset, the BIST
is 0x80000000, which causes BIST error. We skip checking this bit.
The update will be in CZ BKDG 1.05.
The code is tested on AMD/bettong.
Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch
southbridges. The mcp55 code could not find the mainboard's verb table
because the table was not even being compiled in. The sch boards appeared
to have the same issue.
Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate
shrink, so apply it to those too.
Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078
(azalia: Shrink boilerplate)
Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10826
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.
This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.
Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
LDO2 regulator is used as an always-on reference for the droop alert
circuit. Set output voltage to match kernel settings.
CQ-DEPEND=CL:284649
BUG=chrome-os-partner:42305
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c
Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284879
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10900
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:42220
BRANCH=veyron
TEST=Used physical recovery button to enter dev mode on mickey
Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d
Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283546
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Danger has a physical developer mode switch, it was just never
set up. This patch defines it, sets it up in fill_lb_gpios(),
and disables VIRTUAL_DEV_SWITCH.
Note: For now at least, dev mode is a bit wonky on Danger. It's
connected to both a DIP switch and a button. The button is normally
open, pulling dev mode high (defaulting to ON). The switch's "ON"
position will pull the value low, so we invert the value in coreboot
to see the expected behavior. Dev mode is enabled by holding the
button down during boot or by setting switch 2 in the DIP bank to
the ON position.
BUG=none
BRANCH=none
TEST=toggled dev switch on Danger and saw dev screen show up (or
not) as expected
Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318
Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280852
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No need to repeat this in the mainboard code (even if there's only one right
now).
Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10825
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix up all the code that is using / to use >> for divisions instead.
Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10819
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This value is overwritten in the next line.
Change-Id: I622c35b8d78f6b01f2532dd8b40db15b2e888f58
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Stops Linux from complaining:
[0.097286] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
[0.100005] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
[0.100005] ...trying to set up timer (IRQ0) through the 8259A ...
[0.100005] ..... (found apic 0 pin 0) ...
[0.143507] ....... works.
Change-Id: Ic09a6940f80e3da2c1f3c0ef04fb50a4096b7943
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that we have functioning display code for all platforms,
we can just get rid of this ugly hack used on non-Chromebook
veyrons.
BUG=none
BRANCH=none
TEST=built for Brain, Rialto, Mickey, Romy
Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5
Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282049
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This uses VOP_MODE_NONE for display init on veyron_rialto and
adds a mainboard_power_on_backlight() stub so that we can finally
get rid of SKIP_DISPLAY_INIT_HACK.
BUG=none
BRANCH=none
TEST=built for veyron_rialto
Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d
Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282048
Reviewed-on: http://review.coreboot.org/10784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux. Calls to PMIC
functions to enable HDMI power are moved here as well.
BUG=none
BRANCH=none
TEST=with follow-up patches, we now get a dev screen on Brain.
Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013
Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282046
Reviewed-on: http://review.coreboot.org/10778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This avoids any ambiguity or breakage in case the vop_modes get
shuffled around or changed in some future patch or copy+paste job.
Brain and Rialto need some more work done so their devicetree.cb
files will be updated in follow-up patches.
BUG=none
BRANCH=none
TEST=compiled only (for danger, jerry, mickey, romy, speedy)
Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db
Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282610
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
EDP-related hardware modifications for v2:
- BL_EN moved from GPIO7_A3 to GPIO7_A2
- EDP_HPD added to GPIO7_B3
BUG=none
BRANCH=none
TEST=built and booted Danger v2 with EDP panel attached, saw dev
mode screen come up
Change-Id: I47383610082b371a612aced656e56f1bd1cfa098
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b
Original-Reviewed-on: https://chromium-review.googlesource.com/280855
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are all Kconfig symbols that have been removed or renamed.
USE_PRINTK_IN_CAR was removed in commit 8c4f31b3
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision...
DYNAMIC_CBMEM was removed in commit e2b0affd
Remove Kconfig variable that has no effect
MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc
Remove Kconfig variable that has no effect
CACHE_ROM was removed in commit 4337020b
Remove CACHE_ROM.
SMM_MODULES was removed in commit 44cbe10f
smm: Merge configs SMM_MODULES and SMM_TSEG
INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218
soc/fsp_baytrail: Fix use of microcode-related Kconfig variables
CAR_MIGRATION was removed in commit cbf5bdfe
CBMEM: Always select CAR_MIGRATION
REQUIRES_BLOB was removed in commit 70c85eab
build system: Retire REQUIRES_BLOB
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b
uart: Redefine Kconfig options
CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit
afa7b13b - uart: Redefine Kconfig options
Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10766
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since USBDEBUG is not selected by this platform, there is no
benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard
Kconfig. Further, using a 'select' for USBDEBUG_IN_ROMSTAGE
prevents the value from being modified by a user in menuconfig.
Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/10671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART.
Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch fixes up verified boot (vboot2) configuration of all
tegra 124 bases boards in the tree.
Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10761
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Otherwise the Chrome OS build won't succeed.
Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10760
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail
platforms have their own defaults.
Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames
across the directory)
Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10757
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Exynos SoC code and vboot really don't get along and things are not even
in a good shape in Chrome OS' top of tree. Disable but don't rip out the
support functions, so it could be revived.
Change-Id: I982c5a3731b527fd1f1579e9de353819da656452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Initializing timestamps and writing the "start romstage" timestamp already
happens earlier.
One question to sort out is what to do about the migration into cbmem, but at
least this compiles again.
Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A lot changed here between Chrome OS and upstream, and these changes are
needed to reflect that.
Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10723
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot configuration (separate stage or not, which stage loads romstage)
depends on SoC properties (eg. amount of SRAM), not on board specifics, so
move this part of the configuration to the SoC.
Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
romstage requires some button accessor functions for the Chrome OS boot flow.
Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10697
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy.
- board-ID differentiation removed, see mainboard.c
- speedy -> shark rename
BRANCH=None
BUG=None
TEST=Compiled.
Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86
Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276490
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10699
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Not all devices have a lid switch, so we need to state this
somehow. Since the alternative would be to extend get_lid_switch()'s
semantics to become a tri-state (open, closed, N/A), do this
through Kconfig.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273850
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The function was used locally and in ramstage to set some
coreboot tables. It's also needed in romstage to deal with
"lid closed" behaviour.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424
Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273609
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This re-factors SDMMC power on/off to make corrections and take
differences between board versions into account. To avoid similar-
but-different case switch statements in romstage.c and mainboard.c,
power on/off functions for SDMMC are split into their own .c file.
BUG=none
BRANCH=none
TEST=built and booted of micro-SD card on Danger v2
Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519
Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280853
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux.
We'll add EDP/HDMI auto-detection in an upcoming patch.
BUG=none
BRANCH=none
TEST=set vop_mode to 1 in Danger's devicetree.cb and saw
dev mode screen output to HDMI display.
Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71
Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
