Commit Graph

47464 Commits

Author SHA1 Message Date
Raul E Rangel 169302aa7f acpi, arch/x86/smp/mpspec,soc/amd/common: Move MP_IRQ_ flags into acpi.h
The MP_IRQ flags can be used in the MP table and the ACPI MADT table.
Move them into acpi.h to avoid pulling in the full mpspec.h which is
only available on x86.

BUG=b:218874489, b:160595155
TEST=Build

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f1091b7629a6446fa399720b0270556a926401a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 13:08:35 +00:00
Werner Zeh bae8498486 soc/intel/cmn/spi: Separate fast SPI device from generic SPI driver
The fast SPI controller (usually handling the boot NOR flash) is a
different controller type than the generic SPI controllers as it
provides access to the boot flash and usually is not used for generic
SPI slave connections.

Though there is common code for the fast SPI controller it currently do
not uses the PCI driver structure. This patch adds the PCI driver
envelope to the fast SPI driver and moves Apollo Lake as the first
platform to this driver.

Change-Id: I31bf39ec1c622db887dec9ca8623a7f282402849
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 13:07:52 +00:00
Ritul Guru 8da3804430 soc/amd/common/block/psp: Add platform secure boot support
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
only available with NDA customers.

Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-16 12:34:59 +00:00
Felix Held 5481eb3c2e mb/google/guybrush/devicetree: use defines for ComboPhyStaticConfig
Use the existing definitions from FspUsb.h instead of magic values for
the ComboPhyStaticConfig settings in the mainboard's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2707d017909b7516e5d8711c8f4e2914165ed10d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 12:28:46 +00:00
Arthur Heymans 876a1b48f8 arch/x86/postcar_loader.c: Change prepare_and_run_postcar signature
The postcar frame can now be a local variable to that function.

Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16 07:05:59 +00:00
Arthur Heymans ba00d10c41 arch/x86/postcar_loader.c: Reduce the scope of functions
Some functions are only called locally.

Change-Id: I96a4e40a225536f62abb2a15c55d333b8604e8cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16 07:05:46 +00:00
Arthur Heymans 4e619b2c5c drivers/amd/agesa: Use prepare_and_run_postcar
This removes some of the postcar setup boilerplate.

Change-Id: I4f8f92b88ac16dd70ff4878dfc14e676386d4703
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-16 07:05:30 +00:00
Arthur Heymans 796147f5ca soc/amd/stoneyridge: Use common prepare_and_run_postcar
This reduces boilerplate postcar frame setup.

Change-Id: I8e258113c90ee49864ceddf36ea296ba6f83afe4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16 07:05:14 +00:00
Arthur Heymans 46b409da48 arch/x86/postcar: Set up postcar MTRR in C code
Setting up postcar MTRRs is done when invd is already called so there
is no reason to do this in assembly anymore.

This also drops the custom code for Quark to set up MTRRs.

TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set
in postcar & ramstage.

Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 07:05:03 +00:00
Sean Rhodes 645dde7794 util/inteltool: Add support for Gemini Lake
Tested on:
* StarLite Mk III (N5000)
* StarLite Mk IV (N5030)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 07:04:22 +00:00
Kyösti Mälkki 8a80cc8dd0 google/cyan: Clean up write_protect_state()
The commentary was wrong, write_protect_state() is only called
in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is
selected.

Implementation of get_gpio() eventually does the MMIO read, so
BOARD_GOOGLE_CYAN was not a special case.

Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16 07:03:31 +00:00
David Hendricks 90e2adf0d3 src/vendorcode/cavium: Fix guard in bdk-require.h
Change-Id: I5d4ac11d0c9501dd3a753f8f29581552c484ff59
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16 06:55:16 +00:00
David Hendricks 7d0e5fa3ff libpayload: Fix guards in include/{arm,arm64,x86}/arch/barrier.h
Change-Id: Ib4897c4f5837f7f3173d5062eecb893adbe36964
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16 06:55:06 +00:00
David Hendricks c6396a82e9 drivers/ipmi: Fix header guard
Change-Id: Ic1f33ce883443da1c68627e4c1db10871deecd0d
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64364
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 06:54:57 +00:00
Arthur Heymans d9e750c4fd soc/intel/*: Fix up header guards
Change-Id: If9ae375629c8af3d32b4c5493b5d63203e8847aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16 06:54:11 +00:00
Arthur Heymans 08769c6d14 soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with
ASL code.

Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16 06:53:46 +00:00
Tim Wawrzynczak 159520ed78 mb/google/brya: Consistently put void before __weak attribute
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 05:20:40 +00:00
Martin Roth af06e9adea util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]
For some reason, the '\s' syntax is causing an error for me under
freebsd.  It's entirely possible that I'm doing something wrong, but
this change should be fine regardless.

Freebsd's grep, GNU grep, and git grep all handle posix regex classes,
so this change should be transparent.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16 05:18:09 +00:00
Kane Chen be9cef9468 soc/intel/common: Consistently use smbus 7-bit address log format
The "No memory dimm at address" line in get_spd_sn and get_spd fucntion
have different format of SPD address.

get_spd_sn shows a 8-bit address format but get_spd shows a 7-bit
address format when there is no DIMM connected. It can be confusing
when debugging.

Change-Id: I46a006f4024b12d27ae0a933b7c40515034d5d64
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:14:51 +00:00
Maulik V Vaghela 0485ab6612 intelblocks/gpio: Optimize GPIO functions by passing group and pin info
There were 3 different functions in gpio.c file which used to
get gpio group and pin information separately through function
calls.

Since these are static function, we can modify argument to
pass group and pin information from parent/calling function.

This will reduce redundant work of getting information 3 times
separately.

BUG=None
BRANCH=None
TEST=code compiles and correct information is passed to functions.
Check by using pin information on Brya.

Change-Id: Ie92be8c22838ebc5e831be58545e2023eecfff24
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:13:13 +00:00
Reka Norman 48e16f76c5 mb/google/nissa/var/nivviks: Disable PCIe WLAN pins
Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs.

BUG=b:218929856
TEST=Boot to OS on nivviks and check that WLAN still works.

Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:11:29 +00:00
Reka Norman f2f785dbbe mb/google/nissa/var/nivviks: Add support for NVMe and UFS
Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are
only supported on nirwen, an additional nissa variant based on nivviks
and sharing the nivviks coreboot target.

BUG=b:218929856
TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS
will be tested once nirwen boards are available.

Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:11:07 +00:00
Reka Norman e4ebc86a3b mb/google/nissa/var/nivviks: Update GPIOs to support nirwen
Nirwen is an additional nissa reference board which is almost identical
to nivviks, so is reusing the nivviks coreboot variant. However, there
are two GPIO changes, so update the GPIO tables to handle these based on
board_id.

nivviks:
GPP_D6  -> WWAN_EN
GPP_E13 -> NC

nirwen:
GPP_D6  -> SSD_CLKREQ_ODL
GPP_E13 -> WWAN_EN

BUG=b:218929856
TEST=Boot to OS on nivviks

Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:52 +00:00
Reka Norman 1c7f9f914d mb/google/nissa/var/nivviks: Disable pen garage based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen
garage is enabled/disabled as expected.

Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:39 +00:00
Reka Norman f1b8cee5f3 mb/google/nissa/var/nivviks: Disable MIPI WFC based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC
is enabled/disabled as expected.

Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 05:10:11 +00:00
Usha P 49df3cff0d mb/google/brya: Remove Rcomp resistors override for Nissa
This patch sets the RComp resistor values to default values needed.

BUG=b:231202733
TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set
to default values from debug FSP log.
[SPEW ]  Updating Rcomp Targets:
[SPEW ]   RcompTarget[RdOdt]: 48
[SPEW ]   RcompTarget[WrDS]: 30
[SPEW ]   RcompTarget[WrDSCmd]: 20
[SPEW ]   RcompTarget[WrDSCtl]: 20
[SPEW ]   RcompTarget[WrDSClk]: 20

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I2c7a54c49e282446ece77ca406951782282a009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16 05:06:19 +00:00
Terry Chen 62d3ba808d mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota.

BUG=b:231686917
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16 05:03:53 +00:00
Arthur Heymans 6fc12540fc arch/x86/null_breakpoint: Remove handler before jumping to payload
If a payload did any NULL dereferencing it would be broken and jump
back to coreboot code. This fixes the SeaBIOS, FILO and possibly other
payloads too.

Fixes: 3f01cd1453 ("arch/x86: Add support for catching null
dereferences through debug regs")

TESTED on qemu/i440fx.

Change-Id: I80f69b71f4d0fab3126e4b9f8c8dc7737b372174
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64345
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 05:00:31 +00:00
Maulik V Vaghela 38b8bf02d8 intelblocks: Add function to program GPE_EN before GPIO locking
Since coreboot locks GPIO registers after GPIO configuration, OS is not
able to program GPE_EN register to program wake events. This causes
the issue of event not getting logged into event log (since GPE_EN bit
is not set).

GPE_EN register programming is required for the GPIO pins which are
capable of generating SCI for the system wake. Elog mechanism relies
on GPE_EN and GPE_STS bit to log correct wake signal.

This patch add supports to program GPE_EN register before coreboot locks
the GPIO registers. Note that coreboot will only program GPE_EN bits for
GPIO capable of generating SCI.

This will help resolve issue where we don't see wake event GPIO in event
log.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Compile code for Brya and see GPE_EN bits set from the kernel console

Change-Id: I27e525f50c374c2cc9675e77eaa7774683a6e7c2
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 04:58:30 +00:00
Maulik V Vaghela afe840957c soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition
coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.

This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.

Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.

Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 04:57:45 +00:00
Terry Chen 37ffdf3d5c mb/google/crota: Change ELAN touchscreen i2c address and HID
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C

BUG=b:231684121
TEST=local build and tested with ELAN touch screen

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ide005a0681e236c3102090c1c36ab81926849000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16 04:55:12 +00:00
Reka Norman baf22462b7 mb/google/nissa/var/nivviks: Disable SD card based on fw_config
BUG=b:218929856
TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD
card is enabled/disabled as expected.

Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16 04:51:27 +00:00
Reka Norman d88233ecd3 drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15
Ti50 firmware versions below 0.0.15 don't support the firmware_version
register and trying to access it causes I2C errors. Some nissa boards
are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading
the firmware version and select it for nissa. The firmware version is
only read to print it to the console, so it's fine to skip this. This
workaround will be removed once all ODM stocks are updated to 0.0.15 or
higher.

A similar workaround Kconfig was added in CB:63011 then removed in
CB:63158 which added support for separate handling of Cr50 and Ti50.
But we actually still need this workaround until all Ti50 stocks are
upgraded to 0.0.15 or higher.

BUG=b:224650720
TEST=Boot to OS on nereid with Ti50 0.0.14

Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16 04:51:13 +00:00
Eric Lai 6cb787b19a mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIO
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need
to set it as INT in coreboot to make the IRQ work.

BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
  Event type 0 (EV_SYN)
  Event type 5 (EV_SW)
    Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16 04:51:04 +00:00
Kane Chen 2e96eebf01 soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR init
By using mp_run_on_all_cpus_synchronously to run APs MTRR init, it
gurantees the BSP will run post_cpus_add_romcache until all APs finishes
_x86_setup_mtrrs task.

BUG=b:225766934
TEST=Test on redrix and found the MTRR race condition on AP/BSP is gone.

Change-Id: I1fd889f880a0c605e6c739423a434d2adbc12d26
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16 04:49:33 +00:00
Kane Chen c9b1f8a28e cpu/x86/mp_init.c: Add mp_run_on_all_cpus_synchronously
MTRR is a core level register which means 2 threads in one core share
same MTRR. There is a race condition could happen that AP overrides
BSP MTRR unintentionally.

In order to prevent such race condition between BSP and APs, this
patch provides a function to let BSP assign tasks to all APs and wait
them to complete the assigned tasks.

BUG=b:225766934

Change-Id: I8d1d49bca410c821a3ad0347548afc42eb860594
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63566
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 04:49:25 +00:00
Shelly Chang 8b02bd1f8d soc/intel/common/block/smbus: Add smbus block read write functions
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: Ib795f25abe5bbd95555b68af39c637d7c93aa819
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 04:46:51 +00:00
Raul E Rangel 0a5d1d7aae soc/amd/picasso/acpi: Change GPIO controller interrupt to shared
This change matches what we already do for cezanne. It will allow the
GPIO controller to work correctly in windows.

BUG=b:175146875
TEST=Boot windows and verify GPIO controller binds correctly and touch
screen works. Also boot linux and verify touchpad still works.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-16 04:42:53 +00:00
Felix Held 221c15d3a0 mb/amd/chausie/devicetree: add USB PHY configuration
Specify the USB PHY settings in the devicetree instead of relying on the
FSP defaults. The USB PHY configuration for Chausie are taken from the
internal UEFI code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-16 04:39:26 +00:00
Stefan Ott 0d943175f1 mb/lenovo/t60: Add support for ThinkLight
With this patch, the ThinkLight on the ThinkPad T60 can be controlled
through the OS.  This was initially done for the X201 in f63fbdb6:
mb/lenovo/x201: Add support for ThinkLight.

After applying this patch, the light can be controlled like this:

    echo on >/proc/acpi/ibm/light
    echo off >/proc/acpi/ibm/light

Or through sysfs at /sys/class/leds/tpacpi::thinklight

Change-Id: I47f878533d36857d002d2e2605cc8bc7e1d960c9
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-16 04:38:08 +00:00
Eric Lai 586be058f4 lib/spd: Demote log about using default DDR4 params to NOTICE
Demote log level from error to notice. People should aware the SPD
decode might be wrong if it's not the support type.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I55f0968b78baaa2fc9a6bbebf6712fb8bfd349f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-05-16 04:34:59 +00:00
Elyes Haouas 2e96e9441d sb/amd/agesa/hudson/hudson.c: Use BIT() macros
Also, code reformatting to reduce coding style difference.

Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:58:36 +00:00
Elyes Haouas e37806766f sb/amd/*/*/acpi: Reduce stylistic differences
Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:57:51 +00:00
Elyes Haouas 9ca1ef96ae payloads/coreinfo/coreboot_module.c: Remove 'break' after 'return'
Change-Id: Icb60115349ef7c4c35635021784138d45c5a8872
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61954
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 02:56:31 +00:00
Elyes HAOUAS dd75aaf3f5 northbridge/intel/i945: Convert to ASL 2.0
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:55:28 +00:00
Elyes Haouas 90e4d744cc amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTE
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69)
memory buffer personality bytes is located at bytes 102 ~ 116.

Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:53:59 +00:00
Elyes Haouas ae2c045733 payloads/nvramcui/nvramcui.c: Reformat code
Change-Id: If5b4ae7d9f9046e56ca098c0469b503130bc8707
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:49:50 +00:00
Elyes Haouas 3fd719755d cpu/amd: Remove unused <cpu/x86/pae.h>
Found using:
diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/)

Change-Id: I4cab4b66c3d123dbb8a948a5596aa4975b31139b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:41:33 +00:00
Elyes Haouas adec3861be soc/intel/apollolake/romstage.c: Remove unused <cpu/x86/pae.h>
Found using:
diff <(git grep -l '#include <cpu/x86/pae.h>' -- src/) <(git grep -l 'memset_pae\|MEMSET_PAE_\|MAPPING_ERROR\|map_2M_page\|paging_identity_map_addr\|paging_enable_for_car\|paging_set_default_pat\|paging_set_pat\|PAT_ENCODE\|PAT_UC_MINUS\|PAT_WB\|PAT_WP\|PAT_WT\|PAT_WC\|PAT_UC\|paging_set_nxe\|paging_disable_pae\|paging_enable_pae\|paging_enable_pae_cr3' -- src/)

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If0f69fa8fe4a336b4e4d2a148d1e7a911af3c2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:40:55 +00:00
Elyes Haouas db735c478e src: Remove unused <cf9_reset.h>
Found using:
diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<"

Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:40:14 +00:00