Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The use of a NHLT table is required to make audio work
on the skylake SoCs employing the internal DSP. The table
describes the audo endpoints (render vs capture) along with
their supported formats. These formats are not only dependent
on the audio peripheral but also hardware interfaces. As such
each format has an associated blob of DSP settings to make
the peripheral work. Lastly, each of these settings are provided
by Intel and need to be generated for each device's hardware
connection plus mode/format it supports. This patch does not
include the dsp setting blobs.
The current supported connections:
- digital mic array 2 channel
- digital mic array 4 channel
- Maxim 98357 amplifier
- ADI ssm4567
- NAU88L25 headset codec
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built glados. Speakers, headphones, and mic on camera decently
worked.
CQ-DEPEND=CL:*239598
Change-Id: If1a9be97573b9b160893944661790cac7df26fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7
Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313998
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12938
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Intel's SST (Smart Sound Technology) employs audio support
which may not consist of HDA. In order to define the topology
of the audio devices (mics, amps, codecs) connected to the
platform a NHLT specification was created to pass this
information from the firmware to the OS/userland.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Tested on glados. Audio does get emitted and some mic recording
works.
Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c
Original-Change-Id: If469f99ed1a958364101078263afb27761236421
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12935
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=None
BUG=None
TEST=Built and boot on kunimitsu. Check for the PL1 value over
sysfs interface
"/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw".
Load the system with Aquarium 1000 Fish, average FPS should be
meeting target 60 with this change.
Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e
Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314416
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/12934
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Help prevent additional files coming in to the tree with the old
license header.
Change-Id: Idbafc2d8c05f87075083293d27900304c53e13dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel. Unlike many coreboot files,
this file may not be re-licensed as GPL V3.
Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.
ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.
Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12917
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The read and write routines take a number of bytes to write, which
should be 1,2, or 4. We now return an error if an invalid size
is specified.
Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
I tried to handle the checking for the config flag internal to xcompile,
but the config flags don't appear to have been loaded into the
environment by make at that point.
This does update the if to check if the flag is even set before putting
anything into .xcompile though. If the LDFLAG isn't set, there's no
point in appending anything.
Also removes the LP version of the erratum config flag, which was a
copy/paste mistake from $(CONFIG_LP_COMPILER_GCC).
Change-Id: I3d8b0328c85310393a120741a498bc18867a6f54
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12858
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Values are taken from the vendor BIOS of my X200s. Notable effect:
Stops display from flashing during native graphics init / Linux mode
setting.
Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.
Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).
Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of looking for an FMAP at every byte, only search down
to a granularity of 16 bytes, reducing the time for a cbfstool
call by 0.3s when no FMAP is found.
Signed-off-by: Stefan Reinauner <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=time ./cbfstool coreboot.rom add -f locale_de.bin -n locale_de.bin -t 0x50 -c lzma
is 0.3s faster than before.
Change-Id: Icb4937330e920ae09928ceda7c1af6a3c5130ac7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc92d838ba9db7733870ea6e8423fa4fa41bf8fe
Original-Change-Id: Idbaec58a199df93bdc10e883c56675b419ab5b8e
Original-Reviewed-on: https://chromium-review.googlesource.com/317321
Original-Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/12932
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In some occasions, Coreboot may need to include the header file from
3rdparty directory. By adding 3rdparty directory to Coreboot include
path, we can include 3rdparty header file directly.
BRANCH=none
BUG=none
TEST=build pass
Change-Id: I8ed68bd330eae1211736a91b213c5dc0af2f7fa9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d6a86b3488ebbc9d8f5f46e922106b71034e7127
Original-Change-Id: Ib8e9f059f88a8c6767f872af8760e91186ae5ec3
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315021
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
In parse_elf_to_stage(), it uses 32-bit variable to handle address.
The correct address type is Elf64_Addr. Use uint64_t to prevent address
to be truncated.
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I1abcd16899a69b18dd10e9678e767b0564b2846e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebc1aae0ae4ca30802a80a4a4e2ae0c0dad4d88a
Original-Change-Id: I21f8057ddf13e442f1cf55da6702c3449ba0cc35
Original-Reviewed-on: https://chromium-review.googlesource.com/292553
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12927
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.
Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
hashcbfs was spliced in a line early, mixing up 'extract' and 'cbfshash'
help texts.
Change-Id: I86d4edb9eec0685a290b2dd4c2dc45d3611eba9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12922
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I74438e8032c84f4190ef49f306969f7157234001
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The license text that we decided to remove was removed from the headers
of these files, but was still left in the help text. Remove it from
those locations as well.
Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.
Enable MAINBOARD_HAS_LPC_TPM so that they will build.
Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.
Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove duplicate line which sets baseaddress parameter.
Change-Id: Idfbb0297e413344be892fa1ecc676a64d20352bf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12904
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The lint target in the makefile relies there being a script using
this particular naming format, so add a shell script front end to
run the kconfig linter.
Change-Id: I029c1cd3bbf3837c9f1d86c391ae5cabfa53685d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12903
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Checkpatch should be 007.
Change-Id: Ib71c50ad1a63a3a743391cd8fea9f79cd08ef6f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12901
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is an initial check for the coreboot toolchain versions. It
currently checks binutils, gcc, clang, and iasl. The other components
are slightly more difficult to test, but should follow on shortly.
If the toolchain is not the correct version, make will halt with
an error.
Change-Id: I41daf6c4545c01dc21231d78fd081bbcf77c4726
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12846
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.
TEST=built and booted guado with full functionality
Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct wrong spelled "subnit" in help message.
Change-Id: Iadbf483835ee4c1b6e3faa454d1cae2660b99c5e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12905
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There's nothing in these files that needs to be hidden if
GOP support is disabled. Removing this allows skylake to
build when GOP support is turned off.
Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12859
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since only X220 with i7 have the USB3 controller this was
probably overlooked.
Before this patch lspci on Linux would not show the NEC USB 3 controller
as well as the PCI bridge it is behind. After, both the bridge and the
NEC controller can be found in the output:
05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller
(rev 04)
Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331
Signed-off-by: Marian Tietz <mtcoreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/12882
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Instead of printing out a single tool that needs to be installed
each time buildgcc is run, print out the entire list of tools
to be installed, then halt.
Change-Id: I7761760eef3c45ba371f882a4f987408945bb3e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12856
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I think this has a fairly low likelyhood of happening, but if AGESA
can't determine the voltage of the memory, it assignes a value of 255
to the variable that it later uses to read from an 3-value array. There
is an assert, but that doesn't halt AGESA, so it would use some random
value. If the voltage can't be determined, fall back to 1.5v as the
default value.
Fixes coverity warning 1294803 - Out-of-bounds read
Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit
physical address space.
This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.
Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.
Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Aaron Durbin