Commit Graph

33349 Commits

Author SHA1 Message Date
Elyes HAOUAS 7b78cde554 soc/intel/broadwell: Convert to ASL 2.0 syntax
Change-Id: Ie1b36e35c564414a4f9b36e120719857f55b862d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46238
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-07 14:54:16 +00:00
Patrick Rudolph d12f030150 mb/emulation/qemu-q35: Mark TSEG region as reserved
Mark TSEG as reserved, which is done on other platforms as well.

For some reason CorebootPayloadPkg crashes when using the region where
TSEG typically resides, which is basically RAM.
UefiPayloadPkg doesn't show this issue.

Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 18:51:29 +00:00
James Ye a85d4a5a9c sb/intel/{bd82x6x,ibexpeak}: hide MEI if ME inoperable
- Add Kconfig option to hide the Management Engine Interface device so
  the OS doesn't try to access it, if the Management Engine is in an
  inoperable mode, e.g. if me_cleaner is used.

- Also hide the MEI if the ME is in Soft Temp Disable mode.

Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e
Signed-off-by: James Ye <jye836@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 12:33:32 +00:00
Kevin Chiu 5b9c3ddaca mb/google/kukui: Add byte mode/single rank DRAM support for burnet/esche
ID#5: Hynix - H9HCNNNFAMMLXR-NEE (Byte mode)
ID#7: MICRON - MT53E1G32D2NP-046 WT:A (Single rank)

BUG=b:165768895
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
     2. power on test ok

Change-Id: Iaa735c23889860218f6f6571cf0bc0b21b304b51
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-02-06 09:09:40 +00:00
V Sowmya 1b150cb000 mb/intel/shadowmountain: Add bootblock and verstage code
This patch includes the bootblock and verstage changes for
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-02-06 09:09:16 +00:00
Kevin Chiu 72463720a2 mb/google/zork: Adjust Dirinboz H1 I2C CLK
Adjust H1 I2C CLK:
404kHz -> 391 kHz

BUG=b:178656936
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on proto board successfully
     3. measure i2c freq by scope is close to 400kHz

Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-02-06 09:08:44 +00:00
FrankChu 26b0bad671 mb/google/dedede/var/galtic: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:179100924
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-06 09:08:28 +00:00
Angel Pons b70ff52b83 intel: Define `RCBA_LENGTH` in Kconfig and use it
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:08:15 +00:00
Mathew King 6109c2cf83 mb/google/guybrush: First pass GPIO configuriation for Guybrush
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50091
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:06:40 +00:00
Mathew King 10dd775ae3 mb/google/guybrush: Add stubs to configure GPIOs
BUG=b:175143925
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 09:06:30 +00:00
Aamir Bohra 30cca6ca2a drivers/intel/fsp2_0: Add support for MP services2 PPI
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.

This implementation also selects the respective MP services PPI version
supported for SoCs

BUG=b:169196864

Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06 09:06:10 +00:00
Furquan Shaikh 5f262be24c intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
in preparation to allow V1 and V2 versions of MP services PPI.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:57 +00:00
Furquan Shaikh 1a5f25ea7f intel: Drop FSP_PEIM_TO_PEIM_INTERFACE
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.

FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y

and is selected by SoCs that want to enable MP PPI services.

Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:

* Auto-selecting FSP_USES_MP_SERVICES_PPI
  --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
  --> The guard isn't really required. The Kconfig options in this
  file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
  --> Makefile under ppi/ already has conditional inclusion of files
  and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
  --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:42 +00:00
Kyösti Mälkki 0f30063abf soc/intel/broadwell: Conditionally skip PRE_GRAPHICS_DELAY
It was commented that the need for the delay was mainly related
to external displays and only with VBIOS execution. Move the
delay such that it is done only when we actually need to execute
the VBIOS aka option rom.

A delay is currently only defined for librem/purism_bdw in
its Kconfig. As the description of the issue sounds like it
would equally happen on other platforms when VBIOS is involved,
promote the Kconfig visible option to global scope.

Change-Id: I4503158576f35057373f003586bbf76af4d59b3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 07:33:51 +00:00
Kyösti Mälkki 021c621eb0 soc/amd/stoneyridge: Create chipset_power_state in romstage
Move chipset_power_state initialisation from early ramstage
to romstage cbmem hook, like everyone else does.

Change-Id: Ib9189a70996ac6cf4515a0d504eb687941a6b5e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 07:17:05 +00:00
Kyösti Mälkki 8fee9951d3 sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.

They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.

It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.

Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 07:16:16 +00:00
Chris Wang 68d68f1d7c soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
add UPD for RV2 USB3 phy setting adjust.

Note: it only for RV2 silicon and not available for RV/PCO.

Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
	-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
	-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1

BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz

Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 23:36:25 +00:00
Felix Held 4cecca4925 soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib7e47e3ba29d171266792fc1ffa8f18e314dc770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 22:06:19 +00:00
Felix Held 7e703d77b2 soc/amd/cezanne/fch: add ACPI I/O port setup
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 22:05:59 +00:00
Felix Held 757d645cb0 soc/amd/picasso: remove PICASSO_ACPI_IO_BASE Kconfig option
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 22:03:34 +00:00
Kyösti Mälkki 74bc46c4db soc/intel/broadwell: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: Ie3feee0448175db2b6ed4e8e37d92de3af9be371
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 21:00:53 +00:00
Angel Pons 35b601cd71 mb/gigabyte/ga-h61m-series: Drop broken thermal.asl
Was copy-pasted from another board and causes ACPI errors on Linux.

Change-Id: I9d62462fb7ddc788d08489bf82b110aeae6a1ffc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-05 17:46:54 +00:00
Felix Held c86acf4216 soc/amd/cezanne: populate some FSP-M UPDs
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-05 15:44:02 +00:00
Kyösti Mälkki 0589e3ce7f soc/amd/common: Refactor single GPIO programming
Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.

Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 15:33:00 +00:00
Kyösti Mälkki ff730feacc soc/amd/common: Separate single GPIO programming
Do this to reduce indentation a bit. Also it may be desireable
to group GPIO configuration such that some GPIOs are handled
outside program_gpios() call and would not be included in
gpio_list array.

Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42807
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 15:30:23 +00:00
Yu-Ping Wu 7aa5b5ece9 soc/mediatek/mt8192: Use LZ4 compression for MCUs
For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot
process. The loading (plus decompression) time of mcupm.bin and sspm.bin
is consistently reduced by 8ms, respectively.

BUG=b:177389446
TEST=emerge-asurada coreboot
TEST=Hayato booted up
BRANCH=none

Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-02-05 09:42:58 +00:00
Frans Hendriks 739c080eef device/device.c: Print done at end of assign_resources()
First and last printk() log the same string.
Add done at end of function.

BUG = N/A
TEST = Build and boot faceboot FBG1701

Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:42:35 +00:00
Frans Hendriks a9caa50e8a device: correct code style
Revise the following aspects to follow coreboot's coding style:
 - Drop braces for single-statement condition and loop bodies.
 - Use `__func__` to print the current function's name.
 - Reflow pointer dereferences to fit in a single line.
 - Adjust the `*` position in pointer variable declarations.
 - Drop unnecessary `else` statements.

BUG = N/A
TEST = Build Compulab Intense-PC with secure oprom enabled

Change-Id: I780251d946d5bea97658476d61d25555ec768dfc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:42:19 +00:00
Tim Chu 3d6d1075b2 soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed
Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:41:56 +00:00
Tim Chu 40d45996d8 arch/x86/smbios: Correct SMBIOS type 4 max speed
Now smbios type 4 max speed field will use the maximum speed of
processor itself if CPUID value can be accessed. However, this field
should be the maximum processor speed supported by the system. Here
we use smbios_cpu_get_max_speed_mhz only to get correct value.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:41:21 +00:00
Kane Chen 9853e42a8e mb/google/zork: update telemetry settings for Woomax
Improve performance and meet stardust test requirement.
PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586)
PcdSet32(PcdTelemetry_VddcrVddOffset, 0)
PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674)
PcdSet32(PcdTelemetry_VddcrSocOffset, 0)

BUG=b:176156237
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:41:09 +00:00
Elyes HAOUAS 3be5565d5d soc/intel/skylake/acpi/irqlinks.asl: Fix typo in comment
Change-Id: Ifbe012a9867a6814f64abcfe336e5edca19df879
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50269
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:40:53 +00:00
Tim Wawrzynczak ee25a6fb0e mb/google/brya: Add support for Hynix H9HCNNNBKMMLXR-NEE LP4x DRAM
BUG=b:178681161
TEST=abuild

Change-Id: Icccfa3d1659e6c74c14a7372ea39c749a5921c64
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-05 09:40:28 +00:00
Evgeny Zinoviev 262a18ceb2 mb/apple/macbookair4_2: Add ACPI support for EC
Add ACPI support for battery, AC and lid.

I don't have MacBook Air 4,2 to test, but:

- I tested it on 5,2;
- I found decompiled DSDT for 4,2 and compared registers and bits,
  they are the same as on 5,2.

So it should work.

Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:40:17 +00:00
Eric Lai 5b302b2ed2 soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-05 09:39:58 +00:00
Angel Pons 6fb87c2b77 soc/intel/broadwell/pch/lpc.c: Program GEN_PMCON_3 in one write
This is what Lynxpoint does. It is equivalent, but simpler.

Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:39:50 +00:00
Evgeny Zinoviev ab5eb89a6f ec/apple: Add ACPI code for Apple MacBooks
- Move ACPI code for Apple MacBooks to a separate directory to avoid
  its duplication in mainboards
- Add AC and lid implementations for newer generations
- Rewrite old code using the new ASL syntax

Tested on MBA 5,2, MBP 8,1 and MBP 10,1.

Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-05 09:39:31 +00:00
Angel Pons 6e732d34a0 intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.

Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290

Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-05 09:39:08 +00:00
Tony Huang 6e0ca68c82 mb/google/dedede: Create kracko variant
Create the kracko variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:178092096
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_KRACKO

Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-05 09:38:49 +00:00
Felix Held 4fbae5c559 soc/amd/common/block/acpi/pm_state: add missing include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22862c2d29f130c741b4817dac00287ecfc71fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04 21:13:59 +00:00
Felix Held da5553cae4 soc/amd/picasso/fch: add missing iomap.h include
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iea9666fe4f61fb503fee4060a90ec75e2d70c24f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-04 15:27:29 +00:00
John Su f37e8eaa77 mb/google/zork/variants/vilboz: Enable BayHub lv2 driver
Enable this driver along with power saving.

BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:34:12 +00:00
John Su 8fff297ea9 drivers/generic/bayhub_lv2: Add driver for BayHub lv2
Add a driver which puts the device into power-saving mode.

BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:34:06 +00:00
Patrick Rudolph 27d4550430 vendorcode/intel/Makefile: Add x86_64 support
This allows to compile FSP related tools (like the FSP loader) in
x86_64 mode, but it doesn't add support for properly running x86_32
FSP on x86_64. This is handled in a separate patch.

Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-04 10:21:49 +00:00
Patrick Rudolph 31218a4259 drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59

This is necessary to run on x86_64, as pointers have different size.

Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.

Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".

Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-04 10:21:42 +00:00
Angel Pons 37cae54034 nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`
This partially reverts:

- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-04 10:21:06 +00:00
Francois Toguo 522e0dbdaa acpi: Add support for reporting CrashLog in BERT table
Crash Data are collected and sent to the OS via the ACPI BERT.

BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-04 10:21:02 +00:00
Nick Chen 5f30ae3714 mb/google/volteer: update thermal table for Eldrid
1. Add pl4 value
2. Change policies passive with sensor 0 and 1
3. Change granularity value with pl1 and pl2

BUG=b:178768749
TEST=make buildall

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 10:20:28 +00:00
Angel Pons 20ca7ebe31 mb/prodrive/hermes: Use some board settings from EEPROM
Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:

- DeepSx
- USB power in S5
- Power state after G3

Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04 10:19:33 +00:00
Angel Pons 7c7e9a2f16 mb/prodrive/hermes: Define board settings in EEPROM
Hermes has an EEPROM with firmware configuration data. Add definitions
to read and verify the `board settings` from the EEPROM. Subsequent
commits will hook up these EEPROM settings.

Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-04 10:19:26 +00:00