Commit Graph

53740 Commits

Author SHA1 Message Date
Iru Cai 7e28c846c3 mb/hp: Add EliteBook 820 G2
Most of the components of this laptop are tested to work,
which is listed in the documentation.

Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04 21:45:53 +00:00
Elyes Haouas 9f59d2a906 coreboot-jenkins-node/Dockerfile: Upgrade lua5 from lua5.3 to lua5.4
Change-Id: Ic1450f0fa8eb69273aa907dea2eba8f7e7131ef1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:55:45 +00:00
Tom Hiller daf6b8bc76 util/docker/coreboot-sdk: add mrc extraction packages
Add packages required to extract the `mrc.bin` from a ChromeOS firmware
image as per the instructions provided in
https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html

Change-Id: I81ed4ef55f0ba745a8a0a0cc85c2b00360f59297
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67160
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:54:42 +00:00
Martin Roth f1ee2f7dc3 util/docker: refactor out and fix docker cache dir test
The test for the docker cache directory was used by two different
targets, so turn it into its own target.

Add missing $ for whoami commands.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5e1d28110097eb502959e81bafe77faa0fc7fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:54:22 +00:00
Martin Roth 18fd3a2315 util/docker: Update coreboot-sdk-test to coreboot-jenkins-test
The coreboot-jenkins-test docker image takes the coreboot-jenkins-node
docker image and runs a series of tests to verify that things build
properly.

This was original created to test the coreboot-sdk, but build functions
like the documentation have been moved from the sdk image into the
jenkins node, so the test needs to be renamed.

Add the makefile target to the help and phony target list at the same
time.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0e6282bbb163064f177c8e68e7180ba2bdc101f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-04 20:53:47 +00:00
Nico Huber 799e79d166 bootsplash: Add ImageMagick voodoo
The JPEG decoder, that was added many years ago to display a boot-
splash in coreboot, has a few quirks. People used to do some voodoo
with GIMP to convert images to the right format, but we can also
achieve the same with ImageMagick's `convert`. The currently known
constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.

Beside that, we can only display the bootsplash if it completely
fits into the framebuffer. As the latter's size is often decided
at runtime, we can't do much more than offering an option to set
a specific size.

Change-Id: I564e0d89fb46503ff4c11e095726616700009968
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04 20:53:24 +00:00
Fred Reitberger 3bcb7619b4 mb/amd/birman/port_descriptors_phoenix.c: Disable ASPM
Disable ASPM on ethernet, sd card, wwan, wlan, and ssd0 PCI devices.

This reduces kernel error logs such as:
[   15.172613] r8169 0000:01:00.0: PCIe Bus Error: severity=Corrected,
type=Data Link Layer, (Transmitter ID)

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04 20:53:05 +00:00
Karthikeyan Ramasubramanian 647abfd1d4 soc/amd/phoenix: Makefile change to include split hash table
Include multiple hash tables into relevant CBFS.

BUG=b:277292697
TEST=Ensure that all multiple hash tables are part of Myst BIOS image
with PSP verstage enabled.

Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:52:36 +00:00
Karthikeyan Ramasubramanian 2c828436a7 soc/amd/phoenix: Add SVC call to inject v2 hash tables
On mainboards using Phoenix SoC with PSP verstage enabled, to
accommodate growing number of PSP binaries, multiple smaller hash tables
are introduced. Also some hash tables are in V2 format identifying the
concerned PSP binaries using UUID. Add SVC calls to support multiple
hash tables with different versions.

BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that
all the hash tables are injected successfully. Ensure that PSP validated
all the signed PSP binaries using the injected hash tables successfully.

Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:52:20 +00:00
Karthikeyan Ramasubramanian 97e57cfd51 soc/amd/common/psp_verstage: Support multiple hash tables
Currently PSP verstage updates PSP bootloader with one unified hash
table containing hashes for all the signed PSP binaries to be validated.
With growing number of PSP binaries to validate and memory constraints
in PSP, there is a requirement to split and update the hash table into
multiple smaller chunks. Hence change the update_psp_fw_hash_table()
signature such that the hash tables are updated in a chipset specific
way.

BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the
Skyrim BIOS image and confirm that the hash table is identical before
and after this change.

Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:52:07 +00:00
Karthikeyan Ramasubramanian abaca2a399 util/amdfwtool: Introduce support for Hash Table v2
Some stages in bootflow prefer to use 16 bytes UUID instead of
traditional 2 bytes FWID to identify the firmware components they
verify/validate. Hence add version 2 of hash table which identifies
firmware components using UUID. Other than UUID and a reserved field for
alignment reasons, the format of the hash table is very similar to hash
table v1.

BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP Verstage enabled. Ensure that
the hash table v2 is built and installed into BIOS image for the
components that are configured in amdfw.cfg file. Ensure that the
validation by PSP is successful for all the relevant components during
the boot flow.

Change-Id: I2899154086cf8e90c3327178157b07ead034b16e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76586
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 20:51:53 +00:00
Karthikeyan Ramasubramanian 24b5227091 util/amdfwtool: Support multiple firmware identifier types
Currently this tool generates a hash table to verify signed binaries,
with a 2 byte FWID as the only kind of identifier. Going forward some
binaries are going to adopt 16 byte UUID identifiers and more binaries
will follow in the future SoCs. Hence add support for handling multiple
firmware identifier types. While at this remove the unused fwid from the
PSP FW table.

BUG=b:277292697
TEST=Build BIOS image and boot to OS in Myst & Skyrim.

Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04 20:49:55 +00:00
Tim Van Patten 71d60ce506 mb/google/skyrim: Select ACPI_S1_NOT_SUPPORTED
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby.

The wake issue either needs to be fixed, or S1 should not be advertised
as a capability in the ACPI table.

Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not
supported on Skyrim devices. This results in 'standby' being removed
from /sys/power/state.

BUG=b:263981434
TEST=suspend_stress_test
TEST=frostflow-rev2 ~ # cat /sys/power/state
freeze mem

Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04 20:48:11 +00:00
Sukumar Ghorai bd2c252094 mb/google/{rex,ovis}: Disable C1-state auto demotion for rex & ovis
C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.

Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.

Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.

BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.

Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04 14:08:51 +00:00
Felix Held 6b324d9919 soc/amd/common/data_fabric_helper: add comment about cfg_inst_acc_en
Since all indirect data fabric register accesses will be non-broadcast
accesses that target a specific data fabric instance, the
cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set
since that makes the indirect access target only a specific data fabric
instance.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-04 14:07:03 +00:00
Sukumar Ghorai bab976b858 soc/intel/meteorlake: Hook up UPD for C1 C-state auto-demotion
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.

This patch hooks up this parameter to devicetree.

BUG=b:286328295
TEST=Check code compiles & boot google/rex, and correct value has been
passed to FSP.

Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-04 14:05:56 +00:00
Kane Chen 2d8bc345cb soc/intel/mtl: Change default for debug consent from 3 to 6
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in
coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled.

This patch updates the Kconfig help text to meet PlatformDebugOption in
MTL and changes debug consent to 6 in default to provide basic SoC
debug capability.

TEST=Boot to OS on screebo and DBC connection is OK.

Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 14:05:15 +00:00
Maximilian Brune 4202a2cbf6 soc/sifive/fu540/Kconfig: Fix opensbi platform
commit 9a7a677 from opensbi project moved the fu540 platform to generic
code and commit 26998f3 from opensbi removed the old non generic
platform. Therefore opensbi platform needs to change to generic.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04 14:04:13 +00:00
Matt DeVillier 3f0de3d3ea ec/google/chromeec: move TBMC ACPI device under CREC
Tablet motion control is a function of the EC, and under Windows, the
TBMC device needs to be initialized after CREC, or driver init will
fail. The only way to ensure this happens is for TBMC to be a child
device under CREC.

TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers
loaded and orientation switching functional under both OSes.

Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04 14:03:52 +00:00
Krishna Prasad Bhat 6ba83484e6 soc/intel/common: Return CB_ERR when cse_data_clear_request() fails
cse_prep_for_rw_update() should return CB_ERR when
cse_data_clear_request fails. It was modified to CB_SUCCESS in this
commit ad6d3128f8 ("soc/intel/common: Use enum cb_err values")

BRANCH=None
BUG=None
TEST=Verify the system goes to recovery during downgrade when
cse_data_clear_request() fails.

Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-04 04:50:25 +00:00
Pratikkumar Prajapati 5013c60a87 soc/intel/meteorlake: Generate new TME key on each warm boot
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor
Lake SOCs. This config allows Intel FSP to programs TME engine to
generate a new key for each warm boot and exclude CBMEM region
from being encrypted by TME.

Bug=b:276120526
TEST= Boot up the system, generate kernel crash using following
commands:

$ echo 1 > /proc/sys/kernel/sysrq
$ echo "c" > /proc/sysrq-trigger

System performs warm boot automatically. Once it is booted,
execute following commands in linux console of the DUT and confirm
ramoops can be read.

$ cat /sys/fs/pstore/console-ramoops-0

S0ix also tested and found working.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-04 04:33:42 +00:00
Kun Liu 386ef64fb2 mb/google/rex/var/screebo: Add fw_config probe for GL9750 and RTS5227S
Add support for SD card reader GL9750 and RTS5227S

BUG=b:284273384
TEST=emerge-rex coreboot

Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-04 04:16:06 +00:00
Daniel_Peng 74d7192f22 mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCL
Add the new memory support:
Samsung K4U6E3S4AB-MGCL

BUG=b:294151054
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \
     src/mainboard/google/dedede/variants/pirika/memory/ \
     src/mainboard/google/dedede/variants/pirika/memory/\
     mem_parts_used.txt"

Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 03:50:48 +00:00
Elyes Haouas 86f4f2fb34 cpu: Get rid of CPU_SPECIFIC_OPTIONS
Remove dummy CPU_SPECIFIC_OPTIONS.

Change-Id: I267b2a7c6dfc887b572e1b63b0f59fbfa4d20f0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76681
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04 03:00:25 +00:00
Elyes Haouas 33201ab49f docker/coreboot-sdk/Dockerfile: Remove old workaround
Remove old workaround for automake and aclocal.

Change-Id: Ifc00a479fd08d9ee4d97df6da8762bae2d097827
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:36:35 +00:00
Elyes Haouas fda10a44b6 util/docker: Remove manual symlink python3 to python
Debian sid symlinks already python3 to python.

Change-Id: Ibc3b2b047df7e1066624d4dd8aa9664ab1869222
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:35:46 +00:00
Elyes Haouas d2e7c0f30d drivers/intel/gma/Kconfig: Remove unused INTEL_GMA_OPREGION_2_0
Change-Id: I9241d713fb8cc26c768746c8e442b46292036d20
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76694
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:34:11 +00:00
Elyes Haouas 06cb756f02 soc/intel/common/block/cse/Kconfig: Remove unused symbols
Change-Id: I35742721e049102a3e153b857824073a5d257cc3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76693
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:33:56 +00:00
Elyes Haouas 93eeb299c4 soc/intel/xeon_sp/spr/Kconfig: Remove unused MAX_MC_CHN
Change-Id: Ia4011a0f29d360fbe46a5e052e2acb3d23d8ceaf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76695
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:33:21 +00:00
Elyes Haouas 80af4b3ea1 mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPD
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:32:42 +00:00
Elyes Haouas 09f7d67c9a soc/intel/jasperlake: Remove dummy CPU_SPECIFIC_OPTIONS
Change-Id: I5ad1a1bf51bb7a451239252f01a90c1d4d94ba49
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76685
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:29:42 +00:00
Elyes Haouas 2e52f0e243 soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONS
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:29:27 +00:00
Elyes Haouas a56a5c2cf8 soc/intel/tigerlake: Remove dummy CPU_SPECIFIC_OPTIONS
Change-Id: Id268943b9347fdb54e07b55c0a2a18ac77bb3a58
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:27:42 +00:00
Elyes Haouas ef959b72bc soc/intel/xeon_sp/Kconfig: Remove useless USE_FSP2_0_DRIVER
Change-Id: Ic384ee804e217ba79f7e191f122ec61565abfc40
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03 18:26:28 +00:00
Elyes Haouas 24548e4c56 soc/intel/xeon_sp/spr/Kconfig: Remove unused SIPI_FINAL_TIMEOUT
Change-Id: I915e0e942adf33175fdc9fe055fce013824d6c0f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76698
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:25:23 +00:00
Elyes Haouas 4bf1385c6c soc/intel/broadwell/Kconfig: Remove dummy SOC_SPECIFIC_OPTIONS
Change-Id: I4ccb8d38f18cb440f54723cc1f29e25b82dac8ee
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76700
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:24:26 +00:00
Jeremy Compostella ede988fb53 Makefile.inc: Fix typo in comment
Replace FILANAME with FILENAME.

Change-Id: I96388245df406e6b4cb1cd3418f6a32d5b23499f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76890
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 18:20:39 +00:00
Nico Huber 6e133fa470 linux_trampoline: Handle 64-bit framebuffer addresses
To support full 64-bit addresses, there is a new field `ext_lfb_base`
since Linux 4.1. It is unclear, however, how a loader is supposed to
know if the kernel is compatible with this. Filling these previously
reserved bits doesn't hurt, but an old kernel would probably ignore
them and not know that it's handling a clipped, invalid address. So
we play safe, and only allow 64-bit addresses for kernels after the
2.15 version bump of the boot protocol.

Change-Id: Ib20184cf207f092062a91ac3e6aa819b956efd33
Signed-off-by: Nico Huber <nico.h@gmx.de>
Co-authored-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76479
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 17:55:01 +00:00
Kyösti Mälkki 6a50e555fc util/abuild: Add per-build statistics tarfile
Change-Id: Icb9a5bdf94013fe493dc8ec634cf3094bcff2838
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75803
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-03 15:21:22 +00:00
Seunghwan Kim 572db7f4c7 mb/google/nissa/var/pirrha: Generate SPD ID for supported memory part
Add pirrha supported memory parts in mem_parts_used.txt, generate
SPD IDs for them.

1. K3KL8L80CM-MGCT (Samsung)
2. K3KL6L60GM-MGCT (Samsung)

BUG=b:292134655
BRANCH=nissa
TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage

Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 15:09:57 +00:00
Pratikkumar Prajapati 10bd2a27b9 soc/intel/meteorlake: Set UPDs for TME exclusion range and new key gen
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize
when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs
are programmed only when INTEL_TME is enabled.

Bug=b:276120526
TEST=Able to build REX platform.

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 14:18:49 +00:00
Pratikkumar Prajapati 62ceabc4d1 soc/intel/common: Merge TME new key gen and exclusion range configs
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and
TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option
named TME_KEY_REGENERATION_ON_WARM_BOOT.

Program Intel TME to generate a new key for each warm boot. TME always
generates a new key on each cold boot. With this option enabled TME
generates a new key even in warm boot. Without this option TME reuses
the key for warm boot.

If a new key is generated on warm boot, DRAM contents from previous
warm boot will not get decrypted. This creates issue in accessing
CBMEM region from previous warm boot. To mitigate the issue coreboot
also programs exclusion range. Intel TME does not encrypt physical
memory range set in exclusion range. Current coreboot implementation
programs TME to exclude CBMEM region. When this config option is
enabled, coreboot instructs Intel FSP to program TME to generate
a new key on every warm boot and also exclude CBMEM region from being
encrypted by TME.

BUG=b:276120526
TEST=Able to build rex.

Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 12:56:10 +00:00
Won Chung bc1533e089 mb/google: Add more comment on GFX devices for the future reference
Add more details to instruct future boards/models implementers regarding
how GFX devices should be added.

If HDMI and DP connectors are enumerated by the kernel in
/sys/class/drm/ then corresponding GFX device should be added to ACPI.
It is possible that some connectors do not have dedicated ports, but
still enumerated.

The order of GFX devices is DDIA -> DDIB -> TCPX.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-03 12:54:31 +00:00
Rex Chou f232b19e56 mb/google/nissa/var/craaskov: Add overridetree
Add override devicetree based on schematics(ver. 20230714).

BUG=b:290248526
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 12:53:18 +00:00
Michał Żygowski 9ec479de47 soc/intel/alderlake/meminit.c: Guard CsPiStartHighinEct properly
Build issue introduced by patch CB:76418 (commit hash
01025d3ae7) for Google boards.
Patch has not been rebased to latest master and tested before
submission causing the Jenkins jobs to fail.

Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03 11:19:13 +00:00
Michał Żygowski eeba3e7915 src/soc/intel/alderlake: add SOC_INTEL_RAPTORLAKE_PCH_S symbol
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected
by board with RPL-S PCH.

For now only the IoT variant of RPL-S FSP is available for use with
700 series chipsets. Boards with 600 series chipsets can still use
RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU
support.

Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03 10:10:17 +00:00
Michał Żygowski 01025d3ae7 soc/intel/alderlake: Depend RPL-guarded FSP UPDs on FSP_USE_REPO
Only the headers on Intel FSP repository have the CnviWifiCore
present. Options guarded for RPL like: DisableDynamicTccoldHandshake
or EnableFastVmode and IccLimit is also supported by all public FSPs
(except ADL-N for the handshake).

Options like LowerBasicMemTestSize and DisableSagvReorder have to be
guarded when FSP_USE_REPO is not selected, as publci FSPs do not have
these options.

Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE
as dependency on the guarded UPDs to make them available for FSPs
that support them as well. Also prioritize the headers from FSP repo
over vendorcode headers if FSP_USE_REPO is selected.

Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-08-03 09:55:19 +00:00
Eran Mitrani ce7d818254 MAINTAINERS: Add a maintainer for soc/intel/meteorlake and mb/google/rex
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I7f01ee979036071ce7574254101e25b908f8e788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-03 04:30:25 +00:00
Arthur Heymans a07b09ab71 acpi.c: Find FACS using 64bit address fields
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I406b9b470d6e76867e47cfda427b199e20cc9b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-03 01:41:54 +00:00
Arthur Heymans d8f2dcebd8 acpi.c: Swap XSDT and RSDT for adding/finding tables
If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.

This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-03 01:41:40 +00:00