Commit Graph

49758 Commits

Author SHA1 Message Date
Elyes Haouas deb5645644 cpu/intel: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:27:41 +00:00
Elyes Haouas 6a9ae29c05 src/commonlib: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ieba5a5291209e50dc8b3816efb25bb5b2515fa6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:27:10 +00:00
Elyes Haouas ae1ca82e87 arch/x86: Clean up includes
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-26 16:26:31 +00:00
Karthikeyan Ramasubramanian d1130b7ec0 soc/amd/mendocino: Add GSVCD range
Add region/range of SPI ROM to be verified by Google Security Chip
(GSC).

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:54 +00:00
Karthikeyan Ramasubramanian 0a0e7514bb soc/amd/mendocino: Update build rules for PSP BIOS image
Do not compress PSP BIOS image when CBFS verification is enabled.
Otherwise when a file is added to CBFS, cbfstool is not able to find the
metadata hash anchor magic in the compressed PSP BIOS image.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled for
both x86 and PSP verstage.

Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:45 +00:00
Karthikeyan Ramasubramanian e30e4f5450 soc/amd/mendocino: Reserve more space for metadata
With CBFS verification enabled, CBFS file header + file name + metadata
consumes more than 64 bytes. Hence reserve additional space aligned to
the next 64 bytes.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Change-Id: I2b7346e2150835443425179048415f3b27d89d89
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 16:00:32 +00:00
Karthikeyan Ramasubramanian 8d66fb1a70 soc/amd: Add amdfw.rom in coreboot.pre
This change ensures that amdfw.rom binary containing metadata hash
anchor is added before any file is added to CBFS. This will allow to
verify all the CBFS files that are not excluded from verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.

Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 16:00:10 +00:00
Karthikeyan Ramasubramanian da5d0251f5 util/cbfstool: Check for metadata hash in verstage
Metadata Hash is usually present inside the first segment of BIOS. On
board where vboot starts in bootblock, it is present in bootblock. On
boards where vboot starts before bootblock, it is present in file
containing verstage. Update cbfstool to check for metadata hash in file
containing verstage besides bootblock.

Add a new CBFS file type for the concerned file and exclude it from CBFS
verification.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.

Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:58 +00:00
Karthikeyan Ramasubramanian ab82a9f9b4 soc/amd: Add an optional unsigned section in PSP verstage
To enable RO CBFS verification in AMD platforms with PSP verstage,
metadata hash for RO CBFS is kept as part of verstage. This means any
updates to RO CBFS, before WP is enabled, requires updating the
metadata hash in the verstage. Hence keep the metadata hash outside the
signed range of PSP verstage. This means the metadata hash gets loaded
as part of loading PSP verstage while still being excluded from the
verification of PSP verstage.

This change keeps the metadata hash outside the PSP footer data. This
will help to keep it outside the signed range of PSP verstage & aligned
to 64 bytes.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled with
both x86 and PSP verstage.

Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:10 +00:00
Karthikeyan Ramasubramanian f19e461f4f lib/metadata_hash: Include metadata_hash in verstage
On boards where vboot starts before bootblock, build metadata_hash in
verstage. This will allow to enable CBFS verification for such
platforms.

BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 verstage and PSP verstage.

Change-Id: I4269069b66ed66c7b1a47fdef2fd0a8054b2e6a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68134
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:59:02 +00:00
Karthikeyan Ramasubramanian 7835861f9d util/amdfwtool: Add build rules for amdfwread
Add build rules to build amdfwread tool. Also mark this as a dependency
either while building tools or amdfw.rom.

BUG=None
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:37 +00:00
Karthikeyan Ramasubramanian 8b86f21f45 util/amdfwtool/amdfwread: List AMDFW RO binary entries
Add support to walk through PSP L1, PSP L2, BIOS L1, BIOS L2 directories
and list the entries present in them. Accommodate both recovery A/B
layout and normal layout. This is required to identify the location and
size of each entries in the finally built amdfw.rom. This in turn can be
used to perform any platform specific verification on the relevant
components.

BUG=None
TEST=Build and list the contents of AMDFW binary.
/usr/bin/amdfwread --ro-list /build/skyrim/firmware/image-skyrim.bin
Table: FW   Offset     Size
PSPL1: Dir  0x00d97000
+-->PSPL1: 0x48 0x00d98000 0x00001000
    +-->PSPL2: Dir  0x00c30000
        +-->PSPL2: 0x00 0x00c31000 0x00000440
        +-->PSPL2: 0x01 0x00c31500 0x00007580
        +-->PSPL2: 0x02 0x00c38b00 0x00019470
        +-->PSPL2: 0x08 0x00c52000 0x0001f560
        +-->PSPL2: 0x09 0x00c71600 0x00000440
        +-->PSPL2: 0x0b 0x430000041(Soft-fuse)
        +-->PSPL2: 0x0c 0x00c71b00 0x00023100
        +-->PSPL2: 0x12 0x00c94c00 0x00015890
        +-->PSPL2: 0x13 0x00caa500 0x000021c0
        +-->PSPL2: 0x20 0x00cac700 0x00000640
        +-->PSPL2: 0x21 0x00cace00 0x00000030
        +-->PSPL2: 0x22 0x00cad000 0x00001000
        +-->PSPL2: 0x24 0x00cae000 0x00003b60
        +-->PSPL2: 0x28 0x00cb1c00 0x00022890
        +-->PSPL2: 0x2d 0x00cd4500 0x00003100
        +-->PSPL2: 0x30 0x00cd7600 0x0006b550
        +-->PSPL2: 0x3a 0x00d42c00 0x000006d0
        +-->PSPL2: 0x3c 0x00d43300 0x000018c0
        +-->PSPL2: 0x44 0x00d44c00 0x00006610
        +-->PSPL2: 0x45 0x00d4b300 0x00001c70
        +-->PSPL2: 0x50 0x00d4d000 0x00001a00
        +-->PSPL2: 0x51 0x00d4ea00 0x00001020
        +-->PSPL2: 0x52 0x00d4fb00 0x00010180
        +-->PSPL2: 0x55 0x00d5fd00 0x00000600
        +-->PSPL2: 0x5a 0x00d60300 0x00000570
        +-->PSPL2: 0x5c 0x00d60900 0x00000b20
        +-->PSPL2: 0x71 0x00d61500 0x00024710
        +-->PSPL2: 0x73 0x00d85d00 0x00010640
        +-->PSPL2: 0x8d 0x00d96400 0x00000030
        +-->PSPL2: 0x49 0x00d99000 0x00001000
            +-->BIOSL2: Dir  0x00d99000
                +-->BIOSL2: 0x60 0x00d9a000 0x00009924
                +-->BIOSL2: 0x68 0x00da4000 0x00009924
                +-->BIOSL2: 0x61 0x2001000(DRAM-Address)
                +-->BIOSL2: 0x62 0x00dada00 0x00010000
                +-->BIOSL2: 0x63 0x00000000 0x0001e000
                +-->BIOSL2: 0x64 0x00db4200 0x00006310
                +-->BIOSL2: 0x65 0x00dba600 0x000004e0
                +-->BIOSL2: 0x64 0x00dbab00 0x00006180
                +-->BIOSL2: 0x65 0x00dc0d00 0x00000250
                +-->BIOSL2: 0x6b 0x201f000(DRAM-Address)
+-->PSPL1: 0x4a 0x00d98000 0x00001000

Change-Id: Ia1b8f1a2b9bc7dc6925a305cdff1442aaff182cd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66761
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:18 +00:00
Karthikeyan Ramasubramanian 0b6e63220f util/amdfwtool/amdfwread: Handle recovery A/B layout
Upcoming AMD SoCs use recovery A/B layout. Update amdfwread tool to
handle it.

Also add a generic read_header function to read different header types.

BUG=None
TEST=Run amdfwread tool against both Skyrim and Guybrush BIOS images to
dump the Softfuse entry.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I6576eaebc611ab338885aed2ee087bf85da3ca15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:56:04 +00:00
Karthikeyan Ramasubramanian 45257abb79 util/amdfwtool/amdfwread: Fix AMDFW_OPT* bit mask
Optional arguments that involve printing information from the firmware
image is mapped to bit fields with bit 31 set. But instead of just
setting bit 31, bits 27 - 31 are set. Fix AMDFW_OPT* bit mask.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d88669bace45f3332c5e56527516b2f38295a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66573
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 15:55:53 +00:00
Karthikeyan Ramasubramanian 852c5dc101 util/amdfwtool/amdfwread: Update relative_offset function
* AMD_ADDR_PHYSICAL refers to physical address in the memory map
* AMD_ADDR_REL_BIOS is relative to the start of the BIOS image
* AMD_ADDR_REL_TAB is relative to the start of concerned PSP or BIOS
tables

Update the relative_offset implementation accordingly. Though
AMD_ADDR_REL_SLOT is defined it is not used. Removing that to simplify
the relative_offset implementation so that it can be used for both PSP
and BIOS firmware tables. Hence update the relative_offset function
signature as well.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I74603dd08eda87393c14b746c4435eaf2bb34126
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-26 15:55:22 +00:00
Arthur Heymans e33377250c payloads/LinuxBoot: Fix Linuxboot kernel fetching for v6.x
Change-Id: Ic1d407eab8ec4569e02729afb5c71f39ce174401
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68815
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 14:12:20 +00:00
Arthur Heymans ea1e36694d coreboot_tables: Drop uart PCI addr
Only edk2 used this to fill in a different struct but even there the
entries go unused, so removing this struct element from coreboot has
no side effects.

Change-Id: Iadd2678c4e01d30471eac43017392d256adda341
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-26 14:12:06 +00:00
David Wu 7203aa5c2d mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKE
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as kano is using a converged firmware image.

BUG=b:253337338
BRANCH=firmware-brya-14505.B
TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
disable hardware write protect and software write protect,
flash and boot kano in end-of-manufacturing mode to kernel.

Cq-Depend: chrome-internal:5046060, chromium:3967356
Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26 14:11:02 +00:00
Maximilian Brune 401fd381bb mb/prodrive/atlas: Disable S3
The Atlas board has currently the problem that suspending the System
causes the System to freeze. Therefore disable S3, until the cause is
figured out and fixed.

Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26 14:10:40 +00:00
Subrata Banik ea708cd617 mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` config
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake
SoC to Rex mainboard to maintain the symmetry with previous
generation ChromeOS devices (Brya and Volteer).

BUG=none
TEST=Able to build and boot to Google/Rex with USB4 functionality
remaining intact.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-26 14:09:46 +00:00
Arthur Heymans 912a262b7b cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NB
Pre-sandy bridge hardware is likely affected by the sinkhole
vulnerability. Intel sandy bridge and newer has hardware mitigations
against this attack according to
https://github.com/xoreaxeaxeax/sinkhole.

Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-26 07:46:51 +00:00
Martin Roth f95a11eff5 soc/amd: Add framework for Glinda SoC
This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.

I believe that there's more that can be made common, but that work will
continue as both platforms are developed.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-25 18:18:37 +00:00
Lawrence Chang 0a5da517c4 soc/intel/alderlake: Add Raptor Lake device IDs
Add system agent ID for RPL QDF# Q271

TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is
gone

Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-25 17:35:26 +00:00
Frank Wu 749daf360b mb/google/skyrim/var/frostflow: Update devicetree setting
Update devicetree based on the schematic_20221014.

BUG=b:253506651, b:251367588
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68482
Reviewed-by: Chao Gui <chaogui@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-10-25 17:20:21 +00:00
Felix Held 6990cb29ab mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboard
Move the Raydium touchscreen to the baseboard devicetree. Since only the
liara variant uses a level IRQ as I2C devices are supposed to, all other
board variants still override this to use an edge IRQ which were added
as a workaround to make the touchscreen work on the other devices. Right
now it's unclear to me if that edge IRQ workaround was only needed
temporarily and can now be removed, so I'll keep it as it was for now.
If this turns out to be no longer needed on the other variants, the
overrides can be dropped in the future.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25 17:16:42 +00:00
Martin Roth 771806da49 console: Add an SoC-specific post-code call
Add a post-code call that SoCs can hook to output or save in any way
that is specific to that SoC.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-25 17:15:58 +00:00
Martin Roth f6fea4fd07 MAINTAINERS: Update instructions
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0e06ac5f92109757143897f3d331aeea0cefe4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-25 17:03:05 +00:00
Elyes Haouas 8ed5835a14 soc/intel/common: Clean up includes
Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-25 16:26:51 +00:00
Elyes Haouas cbbbb6c79d soc/intel/tigerlake: Clean up includes
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-10-25 16:15:09 +00:00
Matt DeVillier d7d551523d ec/google/wilco/superio: Fix PS2K under Windows
PS2K device needs to be under PCI0, not LPCB, for Windows to
recognize it. Same change was made to ChromeEC previously.

Test: Boot Win11 on Drallion, verify built-in keyboard functional.

Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-25 15:13:54 +00:00
Tim Chu e27e1c1c63 soc/intel/xeon_sp: Add functions to store/restore uart state in smm
When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware
initialization that may interfere with OS. Here we store the state
before console initialization and restore state before SMM exit.

Tested=On not public yet system, after exiting smm, uart console can
still work well.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-10-25 15:12:36 +00:00
Tim Chu 5e5335da68 src/drivers/uart: Add definition of FIFO enabled in IIR
Interrupt Identification Register (IIR) is a I/O read-access register.
Add definition of FIFO enabled for this register so that we can check
whether FIFO is enabled or not.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68566
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 15:11:59 +00:00
Sean Rhodes a52d26f2e5 payloads/edk2: Add the declaration for OBJCOPY
The Shimlayer recipe requires OBJCOPY, so declare it at the top of
the Makefile so this recipe works as intended.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2e04dfe18df6252261836dcdf98f7e8de65287b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-25 15:07:10 +00:00
Werner Zeh cd906960df soc/intel/elkhartlake: Fix incorrect divider for MDIO clock
After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.

Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.

Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25 15:06:18 +00:00
Werner Zeh f61070e87c mb/siemens/mc_ehl1: Disable L1 prefetcher
The highly real time driven application executed on mc_ehl1 has shown
that the L1 prefetcher on Elkhart Lake is too aggressive which in the
end leads to an increased number of cache misses. Disabling the L1
prefetcher boosts up the performance (in some cases by more than 10 %)
in this specific use case.

Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-10-25 15:05:35 +00:00
Werner Zeh d03e896b57 soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher
Depending on the real workload that is executed on the system the L1
prefetcher might be too aggressive and will populate the L1 cache ahead
with data that is not really needed. In the end, this will result in a
higher cache miss rate thus slowing down the real application.

This patch provides a devicetree option to disable the L1 prefetcher if
needed. This can be requested on mainboard level if needed.

Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 15:05:18 +00:00
Rex-BC Chen 7fd9b86eae soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MIT
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so
replace "GPL-2.0-only" with "GPL-2.0-only OR MIT".

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:32:05 +00:00
Bo-Chen Chen c1345d6d70 mb/google/geralt: Configure firmware display for eDP panel
Add eDP panel power-on sequences and initialize the display in the
ramstage.

eDP panel in MT8188 EVB: "IVO R140NWF5 RH".
Panel spec name: R140NWF5 RH Product Specification

Firmware display eDP panel logs:
configure_display: Starting display initialization
SINK DPCD version: 0x11
SINK SUPPORT SSC!
Extracted contents:
header:          00 ff ff ff ff ff ff 00
serial number:   26 cf 7d 05 00 00 00 00 00 1e
version:         01 04
basic params:    95 1f 11 78 0a
chroma info:     76 90 94 55 54 90 27 21 50 54
established:     00 00 00
standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
extensions:      00
checksum:        fb
Manufacturer: IVO Model 57d Serial Number 0
Made week 0 of 2020
EDID version: 1.4

BUG=b:244208960
TEST=see firmware display using eDP panel in MT8188 EVB.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:31:27 +00:00
Bo-Chen Chen f09872c5bd soc/mediatek/mt8188: Update mtcmos settings for display and audio
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are
  required.
- For audio, it requires powering on adsp_ao_pwr_con,
  adsp_infra_pwr_con and audio_pwr_con.
- Add new power domain data `ext_buck_iso_bits` for buck isolation
  control.

BUG=b:244208960
TEST=access display registers successfully.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:30:15 +00:00
Bo-Chen Chen 8a604bdbae soc/mediatek/mt8188: Add eDP support for firmware display
MT8188 supports eDP as internal display interface.

BUG=b:244208960
TEST=emerge-geralt coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25 08:29:31 +00:00
Nathan Lu 4ac8598f4b soc/mediatek/mt8188: Add ddp driver to support eDP output
Add DDP (display data path) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DP_INTF0 directly.
Add ddp gclast and output_clamp settings to MT8188 to support
multi-layer display.

BUG=b:244208960
TEST=emerge-geralt coreboot.

Signed-off-by: Nathan Lu <nathan.lu@mediatek.com>
Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:29:03 +00:00
Bo-Chen Chen 511884e7e8 soc/mediatek/mt8188: Rename SPM register
The SPM register at offset 0x0 is often named as poweron_config_set in
previous MediaTek SoCs. To use common driver, we rename it from
poweron_config_en to poweron_config_set.

BUG=none
TEST=emerge-geralt coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-25 08:28:11 +00:00
Rex-BC Chen d641addf38 soc/mediatek: Add support for input 1P mode of dp_intf
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2022-10-25 08:27:52 +00:00
Bo-Chen Chen 319fce53c8 soc/mediatek: Move DP drivers to common
DP drivers can be shared for both MT8195 and MT8188, so move them to
common folder.

BUG=b:244208960
TEST=emerge-cherry coreboot.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-10-25 08:27:31 +00:00
Elyes Haouas 193e86b814 mb/clevo/tgl-u: Avoid indirect includes
Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-10-24 20:04:15 +00:00
Felix Held 2a09a84f15 mb/google/kahlee: always detect ELAN touchpad
Always detecting the presence of the ELAN touchpad doesn't affect the
functionality, but allows dropping the override for all variants that
have multiple touchpad options.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-24 15:50:46 +00:00
Felix Held 34362d0c0f mb/google/kahlee: use override devicetrees for variants
This helps with deduplicating the identical parts of the variants'
devicetrees.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-10-24 15:50:39 +00:00
Martin Roth fed17f968d MAINTAINERS: Add Matt DeVillier to the release team
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6f5c10618edb87d2dc12c14187c4620d8675a443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-24 13:02:39 +00:00
Elyes Haouas 53e3c2414d Update arm-trusted-firmware submodule to upstream master
Updating from commit id c45d2febb:
2022-10-12 15:56:24 +0200 - (Merge "fix(ufs): retry commands on unit attention" into integration)

to commit id 61fe7826d:
2022-10-18 16:20:05 +0200 - (Merge "feat(fvp): build delegated attestation in BL31" into integration)

This brings in 10 new commits:
61fe7826d Merge "feat(fvp): build delegated attestation in BL31" into integration
cf17f7c45 Merge "chore(rpi3): remove redundant code" into integration
70360382b Merge "docs(maintainers): add NPU driver owners" into integration
60c439435 docs(maintainers): add NPU driver owners
e504ce5fa Merge "fix(versal_net): Enable a78 errata workarounds" into integration
bcc6e4a02 fix(versal_net): Enable a78 errata workarounds
0271eddb0 feat(fvp): build delegated attestation in BL31
6047ab122 Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration
769446a68 fix(versal): enable a72 erratum 859971 and 1319367
2594759d2 chore(rpi3): remove redundant code

Change-Id: Ic32c0889961f529e1762b208ef118a94369c34e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-24 13:01:48 +00:00
Patrick Rudolph e249b1a313 arch/x86: x86_64 implies SSE2 support
Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume
SSE2 is present and enabled when targeting x86_64.

This fixes:
- lzma decompression code is compiled with the -Ofast flag
- 'everything' when compiling with clang.

This mostly affects qemu targets, which did not have this flag selected
yet.

TESTED on qemu.

Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-24 12:16:32 +00:00