Commit Graph

24547 Commits

Author SHA1 Message Date
Jonathan Neuschäfer 27d3402258 arch/riscv: Align trap_entry to 4 bytes, as required by spec
The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.

Add the necessary alignment directive before trap_entry.

Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 20:44:43 +00:00
Jonathan Neuschäfer 601197c768 mb/emu/spike-riscv: Move usage instructions into Kconfig help
... and fix them in the process.

The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.

Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-20 20:44:14 +00:00
Andre Heider feefcca601 soc/nvidia/tegra210: add missing bl31 params to ATF config
The ATF tegra210 platform supports more than the currently used
'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h
in the ATF tree.

Add the missing parameters and set them accordingly. The passed UART id
is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the
same port for console output as coreboot.

Successfully tested with UARTB.

Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-20 20:39:33 +00:00
Andre Heider 92712d361d soc/nvidia/tegra210: set up the clock of the chosen UART
Don't always set up UARTA, but instead honor
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the
chosen UART.

Now the matching clock for the used UART is set up.
(The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which
in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.)

Change-Id: Ife209d42af83459136a019c21c2a069396ab36db
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20 20:36:33 +00:00
Andre Heider 86fd16cc0b soc/nvidia/tegra210: add console UART helper functions
These small helper functions aim at supporting the user setting
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.

Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20 20:35:45 +00:00
Andre Heider c9aa0c3d07 soc/nvidia/tegra210: define missing UART clocks sources
These are required to honor CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx later
on.

Change-Id: I7243812fba6f30f1db4db868b258794e7b248be8
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-20 20:35:15 +00:00
Furquan Shaikh 35972def1d util/cbmem: Re-order regex for "cbmem -1"
In case of console dump for only the last boot, cbmem utility checks
for a list of regex in provided order. When pre-cbmem console
overflows, "Pre-CBMEM <stage> console overflowed.. " message is added
before "... <stage> starting" message. This change fixes the order of
regex in cbmem utility to match this.

Test=Verified on soraka that "cbmem -1" correctly dumps the data
starting from Pre-CBMEM romstage overflowed.

Change-Id: I9c5667bbd02ed3e93ac77a4f42e87d754a062919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-19 22:00:16 +00:00
Daisuke Nojiri f984a05cc7 chromeec: Sync ec_commands.h for CBI tags
This patch syncs ec_commands.h with the one in chromeec.

BUG=b:70294260
BRANCH=none
TEST=Verify SKU_ID and OEM_ID are correctly recognized on Fizz.

Change-Id: I451ec9f6f9d7257915b7d4cb1e5adbee82d107de
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17 04:01:03 +00:00
Daisuke Nojiri c205ae0c6e mb/google/fizz: Wait until display is ready
Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.

With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.

The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.

BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)

Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17 04:00:39 +00:00
Daisuke Nojiri ebb86be9fc chromeec: Add google_chromeec_wait_for_display
The google_chromeec_wait_for_display API checks whether a display is
ready or not. It waits in a loop until EC says it entered DisplayPort
alternative mode or times out in 2 seconds.

BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"

Change-Id: Ieee5db77bd6e147936ea8fc735dcbeffec98c0f8
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-02-17 04:00:26 +00:00
Daisuke Nojiri 476c2c5808 chromeec: Add google_chromeec_pd_get_amode
The google_chromeec_pd_get_amode API checks whether TCPM is in a
specified alternate mode or not.

BUG=b:72387533
BRANCH=none
TEST=See 23746 "mb/google/fizz: Wait until display is ready"

Change-Id: Ib9b4ad06b61326fa167c77758603e038d817f928
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-17 04:00:12 +00:00
Justin TerAvest 3fe3f0409c soc/amd/stoneyridge: Normalize GPIO init
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).

BUG=b:72875858
TEST=Built and booted grunt, built gardenia.

Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-17 00:18:38 +00:00
Naresh G Solanki 5b131e27c5 mb/google/{soraka,poppy,nautilus}: Set psys_pmax to 45W
Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.

BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.

Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
2018-02-16 22:48:50 +00:00
Marshall Dawson 178e65d227 amd/stoneyridge: Move model_15_init.c to cpu.c
Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.

Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-02-16 22:46:48 +00:00
David Hendricks bb90fb55d0 board_status: Make board_status more friendly for local usage
board_status.sh was originally written for use cases where the DUT
is remote, i.e. accessed via serial port or SSH. This lead to some
issues when attempting to run the script on the DUT itself.

This patch attempts to handle the local use case more gracefully.
sudo is used when running the cbmem command, and the '-c' option
can be used to set cbmem path in case it's not in the default path
used by sudo.

Change-Id: I62957678ccae65fc46fd6ddf5ae92983d36cffad
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 22:40:20 +00:00
David Hendricks 0dcfb59220 board_status: Don't fetch dmesg via SSH when run over serial
It doesn't make much sense to try and obtain dmesg via SSH if we're
using the serial port. Serial should only be used to obtain dmesg if
SSH is unavailable.

Change-Id: Iec70e64666f9446cf7e98a0fbcaa1cd5cefd8898
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/21567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 22:40:10 +00:00
Marshall Dawson 82145a1275 amd/stoneyridge: Use generic fixed MTRR setup
Add the X86_AMD_FIXED_MTRRS select back to Kconfig.  This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.

Remove the setup from model_15_init.c because this is duplicated
functionality.

BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT

Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 22:38:58 +00:00
Marshall Dawson c0dbedac43 x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs
AMD's fixed MTRRs have RdDram and WrDram bits that route memory
accesses to DRAM vs. MMIO.  These are typically hidden for normal
operation by clearing SYS_CFG[19] (MtrrFixDramModEn).  According to
BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at
reset, should be set for configuration during POST, then cleared for
normal operation.

Attempting to modify the RdDram and WrDram settings without unhiding
them causes a General Protection Fault.  Add functions to enable and
disable MtrrFixDramModEn.  Unhide/hide as necessary when copying or
writing the fixed MTRRs.

Finally, modify sipi_vector.S to enable the bits prior to writing
the fixed MTRRs and disable when complete.

This functionality is compiled out on non-AMD platforms.

BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT

Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 22:38:50 +00:00
Julien Viard de Galbert ed089376e3 mb/scaleway/tagada: Remove unused board_id
Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:13:15 +00:00
Julien Viard de Galbert 5a2c7969e9 mb/scaleway/tagada: Update GPIO configuration
Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:31 +00:00
Julien Viard de Galbert b424caa25a mb/scaleway/tagada: Remove eMMC configuration
The board does no support eMMC so no need to configure it.

Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:21 +00:00
Julien Viard de Galbert d5a1928527 mb/scaleway/tagada: Remove memory down option
The board does not have memory down, only 2 DDR4 Slots.

Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:13 +00:00
Julien Viard de Galbert 3c5019dfd9 mb/scaleway/tagada: Update HSIO configuration
Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:12:03 +00:00
Julien Viard de Galbert bd9ddbcd33 mb/scaleway/tagada: Update device tree
Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:11:55 +00:00
Julien Viard de Galbert 4f13640572 mb/scaleway/tagada: Copy intel/harcuvar and rename
Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-16 17:11:42 +00:00
Paul Menzel e46ef4c0ba soc/amd/stoneyridge/spi: Use correct conversion specifier
Use the correct conversion specifier `z` for `size_t` to fix the error
below.

```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```

Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 17:10:37 +00:00
Richard Spiegel 126614b87b soc/amd/common/block/pi/amd_init_late.c: Transfer memory info to cbmem
SMBIOS structure type 17 is not being generated because memory info is
not being stored to cbmem. This has to happen after AGESA AmdInitLate
has run, but before SMBIOS is generated. There's a need to convert
format between AGESA generated info, and what is required in cbmem.

Create a procedure that transfers information between AGESA and cbmem,
and call it from agesawrapper_post_device() after AmdLateInit is called.

BUG=b:65403853
TEST=build and run kahlee, verify if SMBIOS structure type 17 is being
generated, and if associated strings are what should be expected.

Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 16:23:59 +00:00
Vincent Palatin a25283d8ae mb/google/zoombini/variants/meowth: enable FPMCU interrupt
Enable the micro-controller interrupt line as a real IRQ.

BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.

Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-16 05:30:27 +00:00
Lijian Zhao e1b8221498 soc/intel/cannonlake: Update GPIO ASL
GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.

BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.

Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 04:35:43 +00:00
Lijian Zhao 20123a8838 soc/intel/cannonlake: Use common PCR ASL
Switch to use common version of PCR asl.

BUG=NONE
TEST=Boot up into chrome OS properly on cannonlake rvp platform.

Change-Id: I4975704434d4743bcc0fb6062115da349166c3a6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-16 04:02:44 +00:00
Bora Guvendik 3f672323b5 soc/intel/common/block/gpio: Change group offset calculation
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.

BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK

Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 03:59:29 +00:00
Lijian Zhao 7e2fe06a46 soc/intel/skylake: Switch to common PCR ASL
Using common PCR asl for skylake/kabylake platform.

BUG=None
TEST=None

Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-16 03:27:59 +00:00
Lijian Zhao c303d74163 soc/intel/common: Add generic PCR asl
Access to PCH Private Configuration Space Register can be addressed via
SBERG_BAR, the method is generic across several generations of Intel
SOC.

BUG=None
TEST=None

Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-16 03:27:36 +00:00
Lijian Zhao b716e55033 soc/intel/cannonlake: Add missing GPIO pin definitions
Fill the missing GPIO pin definitions, includeing community 3.

Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22482
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-16 00:23:04 +00:00
Julius Werner 3faa2c802e libpayload: usbhid: Zero-initialize all parts of usbhid instance struct
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.

Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-16 00:08:26 +00:00
Julius Werner 9ec6928b8c google/gru: Fix GPIO_WP pull and polarity for Scarlet
Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.

BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.

Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-16 00:08:00 +00:00
Seunghwan Kim 3f0c7242c9 mb/google/poppy/variant/nautilus: Enable and configure DPTF
This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.

BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot

Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-15 21:41:51 +00:00
Paul Menzel db9709d67d Makefile.inc: Also print layout at end of build
Currently, at the end of a build `CBFSPRINT` prints the content of all
CBFS regions. This is confusing, as they are identical. To avoid
confusion print the layout beforehand.

> layout [-w] – List mutable (or, with -w, readable) image regions

Change-Id: Ibf03b125ef6dae41c58b8ae867430047778cfff3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-02-15 21:40:31 +00:00
Hannah Williams 2b732a2b4c mb/intel/glkrvp: Add FPF_STATUS section in fmd file
Read cse file was not getting cached and taking about 500ms on every boot.

Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15 21:40:06 +00:00
Paul Menzel 3985112898 cpu/x86/16bit/entry16.inc: Fix typo in comment
Add the missing *r* of the possessive pronoun *your*.

Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-02-15 21:39:38 +00:00
Richard Spiegel e0d306447a drivers/generic/adau7002/adau7002.c: Fix null pointer dereference
Procedures acpi_device_scope() and acpi_device_name() can under certain
conditions return NULL. Check the return before using them.

This fixes CID 1385944
BUG=b:73331544
TEST=Build kahlee.

Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23760
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15 21:39:28 +00:00
Richard Spiegel 405f72952c soc/amd/common/block/s3/s3_resume.c: Check mrc_cache_get_current() return
Procedure mrc_cache_get_current() returns -1 for error, 0 for pass. Do
check the return in procedure get_s3nv_info.

This fixes CID 1385943
BUG=b:73333332
TEST=Build kahlee

Change-Id: I0f6a58380a38d13120e997dcd966423d3c2af091
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15 21:39:16 +00:00
Hannah Williams 5e83e8b130 mb/google/octopus: Add new board
Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.

Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15 21:38:50 +00:00
Gergely Kiss af15268c10 tianocore: fix Makefile to build a custom revision or branch
Kconfig variables TIANOCORE_REVISION and TIANOCORE_REVISION_ID
do not have an effect without this fix, the build process would
checkout the hard-coded stable hash even if these variables are set.

Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512
Signed-off-by: Gergely Kiss <mail.gery@gmail.com>
Reviewed-on: https://review.coreboot.org/22983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-15 18:30:23 +00:00
Werner Zeh f7da8927f6 siemens/mc_bdx1: Show mainboard hardware version on console
Show mainboard version in the console log so that one can easily see it.

Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15 07:33:24 +00:00
Werner Zeh 2012a2357d siemens/mc_bdx1: Enable PCA9538 I/O expander
The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.

Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-15 07:33:16 +00:00
Werner Zeh a45d94ac0b drivers/i2c: Add chip driver for I/O expander PCA9538
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C
bus. Add a chip driver to support this chip.

Beside the pure chip driver two interface functions are provided to read
the state of the pins and write output values to the pins.
As the slave address of this chip is hardware configurable the function
pca9538_get_dev() is used to get the right slave address. This function
needs to be implemented in mainboard code if one needs to use the
interface functions to read and write I/O state.

Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-15 07:33:04 +00:00
Jonathan Neuschäfer a94b112aec mb/*/spd: Use normal binary numbers (0b0010) instead of special format (2b0010)
This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.

Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-14 17:02:56 +00:00
Jonathan Neuschäfer 0017004b06 drivers/i2c/designware: Remove spurious word ("familuar")
Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver")
Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23714
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-14 17:01:55 +00:00
Lijian Zhao f1b1d92854 intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.

TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-14 17:01:25 +00:00