This also drops individual copyright notices, all mentioned authors in
that part of the tree are already listed in AUTHORS.
Change-Id: Ic5eddc961d015328e5a90994b7963e7af83cddd3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This also drops individual copyright notices, all mentioned authors in
that part of the tree are already listed in AUTHORS.
Change-Id: Ic2bab77edaf7ad97b7f3278cb108226a18cf3791
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP
vboot build.
BUG=b:150742950
TEST=Puff can boot with EC EFS with hardware write protect enabled
BRANCH=none
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I0877000b7d277106436831f2d69775c25299da9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Add an option to control this, passing it
through to vboot.
BUG=b:150742950
TEST=none
BRANCH=none
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I697e90748e19d15af154011413b30c0f2a0bf52e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit c8b0f31ca1.
Bumping the FADT table version from 3 to 6 causes
Windows 10 to BSOD with an ACPI BIOS error or simply
fail to boot on multiple platforms (Haswell, Broadwell,
Braswell, Skylake). Revert until the issue can be properly
identified and corrected.
Change-Id: I261d953321df2616a3f1c3460a535b57a8848315
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The cache as ram code will use one form of a non-eviction mode.
Change-Id: I418eb48434aa3da3bf5ca65315bb8c9077523966
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Otherwise there will, after make gitconfig,
be (hidden) shell command failures with 'git commit -s':
gmake: util/lint/check-style: Command not found
gmake: *** [Makefile.inc:632: check-style] Error 127
Change-Id: I3891dee53702ee10e5e44dae408193e49d7a89f1
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38227
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BSD grep (on macOS) doesn't like repeated repetition operators, it
throws the error
grep: repetition-operator operand invalid
This removes the superfluous repetition operator to make the commit-msg
hook work on macOS and other platforms not using GNU grep.
Change-Id: Id0f57d0f14634f7844b889d71342b2982fcadeb2
Signed-off-by: Patrick Elsen <pelsen@xfbs.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The memNTrainFlowControl array is generating Coverity warnings
in multiple places in code where it attempts to write to index 1.
The array is defined as either 2 elements or 1 of NULL depending
on #if (AGESA_ENTRY_INIT_POST == TRUE). This is likely a false
alarm from Coverity (memory should not be training outside of a
POST), but adding a second NULL element for the
AGESA_ENTRY_INIT_POST == FALSE case. Tested on Lenovo G505s.
Change-Id: Iaebe0830471e1854d6191c69cdaa552f900ba7a6
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1357451, 1357452, 1357453
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38176
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Potential for out-of-bounds read. However, this code is not
used on F14, F15tn, or F16kb platforms. As can be seen in
vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple
socket F10 is supported. Tested on Lenovo G505s.
Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
AllocParams.Persist is used uninitialized when calling
HeapAllocateBuffer. This could lead to unpredictable or
unintended results. The f15tn and f16 versions of
AmdS3Save.c have already addressed this by initializing
AllocParams.Persist=0 in the same location in the code,
so adding to f14 only.
Change-Id: I2cbfbc4ad14a861e0cd92f130209b3b0f5b76a17
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Uninitialized variable will contain an arbitrary value left from
earlier computations. This issue has already been addressed
in the f15tn and f16kb versions of this same file, so am
backporting the fix.
Change-Id: Id876107265689e08ad6760e514a4911f32b53da7
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38048
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The generic MemNProgramNbPstateDependentRegistersUnb function is unused,
and generates a Coverity warning of an unused switch case. Only family
specific versions of this function are called elsewhere. Delete unused
function.
Change-Id: I2afc83861f4b3a13bfc1eef4920cd3023e608e94
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Found-by: Coverity CID 1241810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38493
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both T530 and W530 share the same PCI device id of 0166 for the iGPU.
Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a
Signed-off-by: Prasun Gera <prasun.gera@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Looks like it should select it like any other Lenovo xx20/xx30 boards
around.
UNTESTED.
Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These two variables are initialized to zero by default.
Change-Id: I590f601b5297a9bfa93607442d7e0b8d79f1ab51
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Only whitespace changes, minor comments. This helps making diff between
devicetrees shorter.
Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some local functions need renaming to avoid name collision.
Change-Id: I0ca311c12f013e54e23ff0427421bfad0b747ea6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37195
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GNU Make 4.3 doesn't propagate a global .SILENT to sub-processes
anymore. Let's make it explicit to maintain the behaviour we are
used to.
From the changelog:
[SV 54740] Ensure .SILENT settings do not leak into sub-makes
Change-Id: I3de51c245d3344b062dc0fe9c62b8d5c0ac5e67d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It somehow creeps into `make clean`, but is not used at all. Since no
VIA platform remains in coreboot, drop the utility as well.
Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
"amdfam10" is no more.
Change-Id: Ibf4892bb4076eb88b864fc0e894b986bf6f6e5bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38054
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current elog implemetation searches for an active PME status bit by
iterating the PCI devices. On disabled or hidden devices a BUG gets
triggered: BUG: pch_log_rp_wake_source requests hidden ...
This is caused by the use of the PCH_DEV_* macros which resolve to
_PCH_DEV and finally call pcidev_path_on_root_debug.
Disabled devices are skipped already so we can safely use the DEVFNs
instead, circumventing the BUG.
Change-Id: Id126e2c51aec84a4af9354b39754ee74687cefc8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Lock MSR MSR_PKG_CST_CONFIG_CONTROL on all cores, not only the one
handling APM_CNT_FINALIZE.
Tested on HP Z220: FWTS no longer reports this as an issue.
Change-Id: I174d6c6c74fbba47992084cc44ebddf84eeeabd1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Make the variable override for CPU_MICROCODE_CBFS_EXTERNAL_BINS local to
the target. Otherwise, `cpu_microcode_bin +=` lines that are evaluated
after `src/cpu/Makefile.inc` still append to it.
Change-Id: If81f307afc325ff3c1e987e9483ed5e45fdc403e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with Denverton
systems.
Change-Id: I615305da5865bef305f560f5c90482cf0937b25a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Leverage the common sku id space helper encoders.
dedede uses the non-legacy SKU ID space.
squash in,
mainboard/google/dedede: Migrate onto get fw_config helper
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from implementation in sb/intel/common.
Test: build/boot variants of google/{beltino,slippy}
with Tianocore and SMMSTORE enabled
Change-Id: I64f520d17146206b8b9b41fc4f827539c5cfd507
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
unzip might not be installed by default, so it is added as a
dependency in crosfirmware script.
Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc
Signed-off-by: Mete Balci <metebalci@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adds PAD_CFG_NF_BUF_IOSSTATE_IOSTERM macro to configure native function,
iosstate, iosterm and disable input/output buffer. This is used in the
pad configurations for the Kontron COMe-mAL10 module board [1].
[1] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: I7aa4d4dee34bd46a064079c576ed64525fd489e6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable read SAR value from cbfs.
BUG=b:150347463
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards.
Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add an optional commandline flag to define the filename of the resulting
output file. If this flag is not defined, it will behave like before by
using the old filename with a ".new" suffix.
With this additional flag it is not necessary to move the output file at
build-time, and the stdout print "Writing new image to <filename>" makes
more sense in the build context.
Change-Id: I824e94e93749f55c3576e4ee2f7804d855fefed2
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Patrick Georgi