Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: Ide0d48405d85ea2e889916f778e1556287651707
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I8cf021ea5baff05eb5f84cc014612084afe3f858
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14053
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: Iba43630208be02603f4e0de5f62047bb3d23863a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14054
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I6e30a7be510c66fb1aa88314861d95f8ebe80377
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14056
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: Ia210e6832c18270043c0cb21b4881d9c802f3b2b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I40373768595a085bba9a5c934794e128f396828b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14059
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I7a053ac1d8ecc3e443e91daeb406bae0b8c13323
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: Ifc32b251677f8b75ffca224c0c900e9c34c756b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: I1313797d60925cc0627987936199e62073c264d7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:
* drivers/intel
* drivers/pc80
* drivers/dec
Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the coreboot makefiles repeatedly run git to try to set
the KERNELVERSION variable and to fetch the submodules. This happens
three times for every build. By exporting a variable, we can catch
this on recursive makes and not run each of these steps again.
Change-Id: I85ab867b40e80c36bd94d48510ffe3252c6cf93f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This is taken from FILO and slightly enhanced.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ieadd9db3f1013ec1cd9f5a1dc44e17587617f1d1
Original-Change-Id: I961a7ddcd39657c9463806d7b82757eff0a4ac57
Original-Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Original-Reviewed-on: http://review.coreboot.org/190
Reviewed-on: https://review.coreboot.org/14386
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h.
barrier.h is present for x86, arm, and arm64, but not for mips. This
is generating a build error after enabling USB by default on libpayload.
I believe that this slipped through the buiders due to them not getting
cleaned fully. It was caught in the coverity scan and when setting up
a new build server.
Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14391
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
BIST result is already stored by arch/x86/bootblock_ctr0.S in
mm0. Also, eax does not contain BIST result by the time control
reaches bootblock_pre_c_entry. bootblock_crt0.S saves timestamp in mm2
which was being overwritten here. Thus, remove the saving of BIST
result from SoC code.
Change-Id: I65444689cf104c59c84574019f5daf82aab10bc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14381
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
This symbol was added to fix a Kconfig lint error after the
Broadwell DE vendorcode was added. Now that the chipset's in
the codebase, it's no longer needed.
Change-Id: Iedb166129c9265cc2cfcc406d98bde92c1a82d2f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14384
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add Intel Broadwell-DE SOC and Camelback Mountain CRB to the list
Change-Id: I3f0c3ae8b38ecf3c3676fe497ade8b74ba94485d
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14382
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
By selecting this switch in Kconfig one can build complete rom image
including descriptor and ME/TXE.
Change-Id: I7307695008df9a61baba1eb024f1f48be62c53c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/14376
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I missed this license header, and it's causing a build breakage.
Change-Id: If472e5c081bd282f0b482af629d6ec2314a2c329
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14388
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
In northcluster.c, the set_resources member of struct device_operations
is set to NULL. That causes this message on the console:
PCI: 00:00.0 missing set_resources
Eliminate that warning by setting set_resources=DEVICE_NOOP.
Change-Id: I4c6c07fd40b180ca44fe67c4a4d07318df10c40f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14366
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
An unsigned enum expression is always strictly positive;
Comparison with '>= 0' is a tautology, hence remove it.
Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8207
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:
- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
per-board copy pasta)
Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
[pg: separated out from the combined commit that added both SoC and
board. Added board_info.txt that will be added downstream, too.]
Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/14279
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Datasheet
https://www.exar.com/content/document.ashx?id=21368
Add support for Exar chip used on a custom board
that was designed to connect to the Olive Hill Plus
development platform. The register dump was verified
on the Olive Hill Plus platform.
Change-Id: Ibd3e13eefb706bd99b6e5b38634f6855b39848ab
Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com>
Reviewed-on: https://review.coreboot.org/14367
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.
Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.
Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some ld versions seem to merge the .zeroptr section (NOLOAD, address 0)
with some debug sections (NOLOAD, address 0) which makes the build
explode when the debug sections are then stripped (including the zeroptr
symbol).
Just define zeroptr to be 0, no sections needed, to avoid this
"optimization".
Checked the objdump -dS of code using it that the accesses look sane.
Change-Id: Ia7cb3e5eae87076caf479d5ae9155a02f74b5663
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is a lot of generic code in the 8250 driver that should
be available for non-8250 systems with serial ports as well.
Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Store both the version number and git hash in the file name
when copying the buildgcc script to the destination directory.
Also, fix the quoting in the lines touched anyways, and move the
script to $TARGETDIR/share/
Change-Id: Ib37dc2be57ee7f0ae18a0b954f537f8b4c2db9d0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14347
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Testing dev->chip == NULL when dev == NULL doesn't make sense (and gcc
thinks that's undefined behavior which should be rewarded with a trap).
Change-Id: I801ce3d6b791fdf96b23333432dee394aa2e2ddf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Initial files to support Camelback Mountain CRB. This board uses
Broadwell-DE code which is based on FSP 1.0. Change is based on
Broadwell-DE Gold release.
Windows 7 and Fedora 21 have been verified using SeaBIOS payload,
also Fedora 21 with U-Boot payload.
Change-Id: Ie249588b79430084adeebbcdd8b483d936c655e3
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14015
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As Aaron pointed out, the old definition made the compiler emit two
memory accesses, to 0 (for derefencing) and then reading at whatever
address could be read from there.
Change-Id: I5cdd53f5bd2d2397c43f09f3e5fa46be08744b01
Found-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This should help catch cases where the AML is not correct.
Change-Id: I48efb9ed0b62b3e17dcf3045ef9c32d813a412bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14340
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On specific revisions of the ASUS KGPE-D16 (> 1.03G) there is a
high (< 1:10) chance of lockup from spurious HW monitor IRQs
during LPC configuration. This was originally erroneously identified
as a bug within the SP5100 southbridge due to serial console buffering
moving the hang slightly before HW monitor setup. It is currently
unknown how changing the CBFS layout / code size was able to alter
the frequency of the lockup occuring; this odd characteristic made
debugging extremely difficult, and it also indicates testing
across multiple PCB revisions will be neded to verify that the
bug has been completely resolved.
It is highly likely that the KCMA-D8 is also affected. As there
does not seem to be a reason to keep the HW monitor IRQ enabled,
simply disable it on both mainboards.
This configuration has passed burn-on power cycle testing with
no lockups noted. All other tests noted a lockup in under 25
power cycles or so, with failure typically occuring in under 5
power cycles; the affected Rev. 1.04 KGPE-D16 has cycled 25 times
times using this patch with only one failure finally noted. This
final failure may have in fact been related to SP5100 Erratum 18
as the frequency is more in line with the errata document guidelines.
Change-Id: Ie9f4f37d2c7dfad0a02daff8b75cd2a1e6f1b09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14333
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Most people use USB keyboards.
Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: https://review.coreboot.org/7540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
cat /sys/power/state should show supported sleep states as freeze and
mem where freeze is "Suspend to Idle" and mem is "Suspend to RAM"
Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Do not disable warnings about unused but set variables to further
improve the code quality.
Change-Id: I25fa29ac42c9d09596d03f11fb01f31635a62a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/3981
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Changes in visible behaviour:
- The default make target doesn't run the tests anymore
- All generated files are stored under util/romcc/build/
(or $BUILD_DIR)
Change-Id: If003240742eb1902a6e9b337cdee299d7d66ee06
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.
Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Martin Roth