Commit Graph

43848 Commits

Author SHA1 Message Date
Patrick Georgi 116b144930 util/kconfig: Simplify dependencies for parser.tab.*
With parser.tab.h depending on parser.tab.c it's possible for make
to initiate the creation of parser.tab.c, then try to compile it,
even though parser.tab.h is still missing.

This isn't normally an issue yet because bison creates them both at
a time but with pre-compiled files this will become a problem.

Pattern rules support (until recently as a special case that no other
type of rule could implement) multiple targets that are actually
treated as "one command creates multiple output files" so use that
to state the relationship properly.

Change-Id: I4aa7eca9d3123808e0665a15a99c04fac7384940
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13 14:49:15 +00:00
Raul E Rangel a96482acd3 arch/x86/boot: Add missing include
This file uses the asmlinkage macro.

BUG=b:179699789
TEST=build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id5b73c174aa946b8205b4172609729b0548cbd8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13 14:18:43 +00:00
Raul E Rangel b0be267c44 soc/amd/common/block/cpu: Add missing include
We use cpuid_eax to get the cpuid family.

BUG=b:179699789
TEST=build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13 14:17:15 +00:00
Jakub Czapiga 29faa8a5a2 tests/stubs/console: Allow enabling printk to print to stdout
By adding TEST_PRINT=1 to <test-name>-config field or by passing it as
a parameter to make one can enable printing in printk() and vprintk().
This can be helpful when developing unit tests.
Note, that to effectively enable or disable printk() printing to stdout,
test(s) have to be recompiled.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ibdec8bb128f42ba4d9cb8bbb4a8c5159a2b52ac5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-09-13 14:00:57 +00:00
Brandon Breitenstein c54e22c589 mb/adlrvp: Add new ADL P board variant for MCHP1727
Add new board variant to enable MCHP1727 Modular EC Card on RVP

BUG=b:179214042
BRANCH=none
TEST=emerge brya and verify that adlrvp_p_mchp images boot

Change-Id: I9dc96ad5c5db21fedbe480d19fcae8434d3bd169
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56839
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:59:45 +00:00
Angel Pons d56d2a86ed util/sconfig: Extract handling of SMBIOS data
Move the code that handles devices' SMBIOS data into a helper function.

Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57369
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:58:20 +00:00
Angel Pons 39e029768b util/sconfig: Always generate SMBIOS CPP guards
Manually maintaining a list of fields just to avoid printing some
unnecessary CPP guards isn't worth the maintenance burden. Instead,
always generate these guards, even if they guard nothing.

Change-Id: I6c84180d83ac39a895e02d196acb7074eb052d7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57459
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13 13:55:59 +00:00
Angel Pons 8b98f8bf07 SMBIOS: Skip `get_smbios_data` for disabled devices
If a device is disabled, do not call the `get_smbios_data` code.

Change-Id: I8960f869e0864f7c82d5fe507f96b62cbd045569
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13 13:54:39 +00:00
Angel Pons 6a73b2466f SMBIOS: Allow skipping default SMBIOS generation
The call to the `get_smbios_data` device operation is followed by
calls to unconditional default functions, which lacks flexibility.
Instead, have devices that implement `get_smbios_data` call these
default functions as needed.

Most `get_smbios_data` implementations are in mainboard code, and are
bound to the root device. The default functions only operate with PCI
devices because of the `dev->path.type != DEVICE_PATH_PCI` checks, so
calling these functions for non-PCI devices is unnecessary. QEMU also
implements `get_smbios_data` but binds it to the domain device, which
isn't PCI either.

Change-Id: Iefbf072b1203d04a98c9d26a30f22cfebe769eb4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13 13:54:03 +00:00
Jingle Hsu 869e90a3d4 arch/x86/smbios: Add support for large memory capacity in type 16
Avoid SMBIOS type 16 Maximum Capacity showing incorrect
information when value of maximum capacity exceeds 32 bits by
extending the type.

Handle 0x0009, DMI type 16, 23 bytes
Physical Memory Array
	Location: System Board Or Motherboard
	Use: System Memory
	Error Correction Type: Single-bit ECC
	Maximum Capacity: 4 TB
	Error Information Handle: Not Provided
	Number Of Devices: 6

Tested=On OCP Crater Lake, the SMBIOS type 16 shows expected
Maximum Capacity.

Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: Iaa79cc587808f1eab0a48e2ce1dab089e84e9721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Daocheng Bu <daocheng.bu@intel.com>
2021-09-13 13:50:04 +00:00
Julius Werner c1b98a43ae spi-generic: Print an error when trying to use a non-existent bus
...because I just spent hours chasing a refactoring bug that would have
been way more obvious with a little more error transparency in here.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3354ff0370ae79f05e5c37d292ac16d446898606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-13 13:49:00 +00:00
Rob Barnes 4c66daaadd device/dram: Add addtional LPDDR4 speed grades
Add additonal LPDDR4 speed grades. This is needed because the limited
set has casued confusion when the reported speed did not match
expectations. There does not seem to be a definitive list of LPDDR4
speed grades, so this list is derieved from JEDEC 209-4C and a survey
of commonly used LPDDR4 speed grades.

BUG=b:194184950
TEST=Boot, dmidecode -t 17 reports correct speed
BRANCH=None

Change-Id: Ie7706fd4ad5a7df68c07b8ca43261429ba140c61
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-09-13 13:47:31 +00:00
Seunghwan Kim 845488d232 mb/google/dedede/var/bugzzy: Generate SPD ID for K4U6E3S4AA-MGCR
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AA-MGCR (Samsung)

BUG=b:192521391
BRANCH=dedede
TEST=Build and boot bugzzy board

Change-Id: Ic0b02559c671845a73a71bd57cd7237850c76645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13 13:45:45 +00:00
Patrick Rudolph 63df43d715 mb/prodrive/hermes: Hook up P2SB and PMC in devicetree
Fixes commit bd5b4aa683
"soc/intel/cannonlake: Switch PMC to use device callbacks" as it
requires the PCI device 1f.2 to be present in the devicetree.
It was missing for this mainboard and caused a boot failure.

Change-Id: Iaf508b2d955578efa2a266af50c568f5c0a47aaf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-09-13 09:49:51 +00:00
Xin Ji 48ae111ca8 drivers/analogix/anx7625: prevent video clock jitter on IVO panels
The MIPI source video data has a large variation (e.g. 59Hz ~ 61Hz),
anx7625 defines K ratio for matching MIPI input video clock and
DP output video clock. A bigger k value can match a bigger video data
variation. IVO panel has smaller variation than DP CTS spec, so decrease
k value to 0x3b.

BUG=b:194659777
BRANCH=none
TEST=Display is normal on Asurada

Change-Id: If3a09811999babda45e9a9a559dd447920109204
Signed-off-by: Xin Ji <xji@analogixsemi.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-13 06:59:20 +00:00
Subrata Banik 3d469fad97 mb/google/brya: Replace white space with tab
This patch unifies line indentation.

Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-11 18:51:59 +00:00
Hung-Te Lin e5cf666b9a mb/google/asurada: fine tune the data lane trail for ANX7625
The ANX7625 display bridge requires customized
hs_da_trail time.

This patch is based on CB:51433 (commit 6482b16,
"mb/google/kukui: fine tune the data lane trail")

BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I0eedb8fa6a1b3dfd9619c7cbf755c9c4071a8484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-09-11 08:04:28 +00:00
Zanxi Chen 2ef4b7ed18 mb/google/trogdor: Add mipi panel for mrbland
Add mipi panel support for mrbland
- Setup gpio and modify LCD sequence.
- Use the following panel for mrbland:
  AUO B101UAN08.3
  BOE TV101WUM-N53
- Use panel_id to distinguish which mipi panel to use.

BUG=b:195516474,b:197300875,b:197300876
BRANCH=none
TEST=emerge-strongbad coreboot

Change-Id: Ib7cd2da429b114bf6bad5af312044a0f01319b46
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57336
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-11 01:54:35 +00:00
Julius Werner 4757a7ea33 mipi: Make panel init callback work directly on DSI transaction types
Our MIPI panel initialization framework differentiates between DCS and
GENERIC commands, but the exact interpretation of those terms is left to
the platform drivers. In practice, the MIPI DSI transaction codes for
these are standardized and platforms always need to do the same
operation of combining the command length and transfer type into a
correct DSI protocol code. This patch factors out the various
platform-specific DSI protocol definitions into a single global one and
moves the transaction type calculation into the common panel framework.

The Qualcomm SC7180 implementation which previously only supported DCS
commands is enhanced to (hopefully? untested for now...) also support
GENERIC commands. While we're rewriting that whole section also fix some
other issues about how exactly long and short commands need to be passed
to that hardware which we identified in the meantime.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-09-11 01:42:47 +00:00
Ronak Kanabar ab7006e4c4 soc/intel/alderlake: Align board type as per FSP v2347_00
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes
BOARD_TYPE_SERVER value to 8.

BUG=b:199359579
BRANCH=None
TEST=Build and boot brya

Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-10 23:00:47 +00:00
Ronak Kanabar 91df11242d vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2347_00
The headers added are generated as per FSP v2347_00.
Previous FSP version was v2265_01.
Changes include:
- UserBd UPD description update in FspmUpd.h

BUG=b:199359579
BRANCH=None
TEST=Build and boot brya

Change-Id: I5e4dd58e5fb1a744b035a4de96986053a02610d3
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10 23:00:26 +00:00
Rob Barnes 9cdc72a3d8 mb/google/guybrush: Invert USB descriptions in devicetree
The USB descriptions are flipped. Fix by inverting the USB descriptions
in devicetree.

BUG=None
TEST=Build
BRANCH=None

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I4b33f4de137536c5f3592380da15f6b3a3633bf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57538
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 22:59:38 +00:00
Rob Barnes 058048c00c mb/google/guybrush: Document USB mapping in devicetree
Add a short documenting comment to each usb entry in devicetree so it is
clear which function each usb port maps to.

BUG=None
TEST=Build
BRANCH=None

Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56725
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 22:58:28 +00:00
Ricardo Quesada b28a035ea0 elog: move MAX_EVENT_SIZE to commonlib/bsd/include
Moves MAX_EVENT_SIZE to commonlib/bsd/include, and renames it
ELOG_MAX_EVENT_SIZE to give it an "scoped" name.

The moving is needed because this defined will be used from
util/cbfstool (see next CL in the chain).

BUG=b:172210863
TEST=compiles Ok

Change-Id: I86b06d257dda5b325a8478a044045b2a63fb1a84
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 22:53:19 +00:00
Ricardo Quesada 49a96a9463 elogtool: add "clear" command
Adds "clear" command to cbfsutil/elogtool tool.
"clear" clears the RW_ELOG region by using either:
 * flashrom if no file is provided
 * or using file write if an input file is provided.

The region is filled with ELOG_TYPE_EOL. And a
ELOG_TYPE_LOG_CLEAR event is inserted.

Additionally, it does a minor cleanup to command "list", like:
 * use buffer_end()
 * add "list" to the cmds struct
 * and make elog_read() very similar to elog_write()

Usage:
$ elogtool clear

BUG=b:172210863
TEST=elogtool clear && elogtool list
     elogtool clear -f invalid.raw
     elogtool clear -f valid.raw

Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-09-10 22:53:05 +00:00
Tim Wawrzynczak 6db0f04fa2 soc/intel/common: Delete pep.asl
After switching to runtime generation of the Intel Power Engine (PEPD)
device, this file is no longer required.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I2444433f08bfda6f79589a397a2ad2b5a3ecb0ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:58:36 +00:00
Tim Wawrzynczak 277334e9f2 soc/intel/skylake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch skylake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7c7cb424278946a9767ea329d18fb03d4e57dce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:58:23 +00:00
Tim Wawrzynczak 6c6eb652d5 soc/intel/common: Add Intel Power Engine support to discoverable PMC
In order to get rid of pep.asl, skylake also needs to support runtime
generation of the Intel Power Engine, therefore add this support to
devices that have a discoverable PMC as well.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4bf0c4a338301b335fa78617e0f2ed5a9f4360ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:58:08 +00:00
Tim Wawrzynczak 46c5f8f1d6 soc/intel/elkhartlake: Switch to runtime generation of Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch elkhartlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:57:43 +00:00
Tim Wawrzynczak 77b36abcf6 soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch jasperlake boards to this method.

soc/intel/jasperlake: Switch to acpigen PEPD

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10 21:57:35 +00:00
Tim Wawrzynczak 6d44437ec1 soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch cannonlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10 21:57:20 +00:00
Tim Wawrzynczak bd5b4aa683 soc/intel/cannonlake: Switch PMC to use device callbacks
Now that the PMC device is marked as hidden in devicetrees, the device
callbacks can be used instead of BOOT_STATE_INIT_ENTRY callbacks.

Note that this moves PMC initialization from BS_DEV_INIT_CHIPS to
BS_DEV_ENUMERATE, which aligns with other Intel SoCs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If292728ad975ba803fed6abea879f6f634470a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:54:44 +00:00
Tim Wawrzynczak b7b5115360 cannonlake mainboards: Set PMC as hidden in devicetree
FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.

TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-10 21:54:23 +00:00
Tim Wawrzynczak 72d94026ce soc/intel/tigerlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch tigerlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8e97c589273e934e89d69d8829680b9cac1ff9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:54:01 +00:00
Tim Wawrzynczak 90f9cbbfc4 soc/intel/tigerlake: Move LPM functions to new file
The LPM enable mask is useful to have in more than one place, therefore
more the get_disable_mask() function and its helpers to lpm.c

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:53:48 +00:00
Tim Wawrzynczak 5faee2ed0f soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch alderlake boards to this method.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 21:53:32 +00:00
Tim Wawrzynczak 2eb100dd12 soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM
method. This allows the ACPI tables to expose device/IP power states
requirements for different system low power states

BUG=b:185437326
TEST=Along with following patch on brya0 after resume from s0ix,
cat /sys/kernel/debug/pmc_core/substate_requirements
                       Element |    S0i2.0 |    S0i3.0 |    Status |
               USB2PLL_OFF_STS |  Required |  Required |       Yes |
   PCIe/USB3.1_Gen2PLL_OFF_STS |  Required |  Required |       Yes |
          PCIe_Gen3PLL_OFF_STS |  Required |  Required |       Yes |
               OPIOPLL_OFF_STS |  Required |  Required |       Yes |
                 OCPLL_OFF_STS |  Required |  Required |       Yes |
               MainPLL_OFF_STS |           |  Required |           |
               MIPIPLL_OFF_STS |  Required |  Required |       Yes |
         Fast_XTAL_Osc_OFF_STS |           |  Required |           |
           AC_Ring_Osc_OFF_STS |  Required |  Required |       Yes |
               SATAPLL_OFF_STS |  Required |  Required |       Yes |
          XTAL_USB2PLL_OFF_STS |           |  Required |       Yes |
                   CSME_PG_STS |  Required |  Required |       Yes |
                   SATA_PG_STS |  Required |  Required |       Yes |
                   xHCI_PG_STS |  Required |  Required |       Yes |
                  UFSX2_PG_STS |  Required |  Required |       Yes |
                    OTG_PG_STS |  Required |  Required |       Yes |
                    SPA_PG_STS |  Required |  Required |       Yes |
                    SPB_PG_STS |  Required |  Required |       Yes |
                    SPC_PG_STS |  Required |  Required |       Yes |
                   THC0_PG_STS |  Required |  Required |       Yes |
                   THC1_PG_STS |  Required |  Required |       Yes |
                 GBETSN_PG_STS |  Required |  Required |       Yes |
                    GBE_PG_STS |  Required |  Required |       Yes |
                   LPSS_PG_STS |  Required |  Required |       Yes |
                   ADSP_D3_STS |           |  Required |       Yes |
                  xHCI0_D3_STS |  Required |  Required |       Yes |
                  xDCI1_D3_STS |  Required |  Required |       Yes |
                     IS_D3_STS |  Required |  Required |       Yes |
                GBE_TSN_D3_STS |  Required |  Required |       Yes |
             CPU_C10_REQ_STS_0 |  Required |  Required |       Yes |
                CNVI_REQ_STS_6 |           |  Required |       Yes |
                 ISH_REQ_STS_7 |           |  Required |       Yes |
       MPHY_Core_DL_REQ_STS_16 |  Required |  Required |       Yes |
      Break-even_En_REQ_STS_17 |  Required |  Required |       Yes |
       Auto-demo_En_REQ_STS_18 |  Required |  Required |       Yes |
    Int_Timer_SS_Wake0_Pol_STS |  Required |  Required |           |
    Int_Timer_SS_Wake1_Pol_STS |  Required |  Required |           |
    Int_Timer_SS_Wake2_Pol_STS |  Required |  Required |           |
    Int_Timer_SS_Wake3_Pol_STS |  Required |  Required |           |
    Int_Timer_SS_Wake4_Pol_STS |  Required |  Required |           |
    Int_Timer_SS_Wake5_Pol_STS |  Required |  Required |           |

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56005
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:56:54 +00:00
Felix Singer 593941b600 util/liveiso/console.nix: Remove unneeded argument body
Change-Id: Iebd994a46e870e42431d0fc71dd14b1c2b01f9aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57536
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:08 +00:00
Felix Singer 46e109f274 util/liveiso: Disable strict checking of access to MMIO memory
Change-Id: Ie859490d3cb3b8c56437cbd6c3e46525c580d3f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57535
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 20:09:02 +00:00
Tim Wawrzynczak 64246480a6 soc/intel/common/block/acpi: Move pep.asl to acpigen
There is a use-case for generating the AML bytecode at runtime for the
Intel Power Engine device, which comes in a followup patch.

BUG=b:185437326
TEST=verified on google/brya and google/dratini by dumping SSDT and
verifying the PEPD device matches what was previously in the DSDT:
    Scope (\_SB.PCI0)
    {
        Device (PEPD)
        {
            Name (_HID, "INT33A1")
            Name (_CID, EisaId ("PNP0D80")
            Method (_DSM, 4, Serialized)
            {
                ToBuffer (Arg0, Local0)
                If ((Local0 == ToUUID ("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")))
                {
                    ToInteger (Arg2, Local1)
                    If ((Local1 == Zero))
                    {
                        Return (Buffer (One)
                        {
                             0x63
                        })
                    }
		    If ((Local1 == One))
                    {
                        Return (Package (0x01)
                        {
                            Package (0x03)
                            {
                                \NULL,
                                Zero,
                                Package (0x02)
                                {
                                    Zero,
                                    Package (0x02)
                                    {
                                        0xFF,
                                        Zero
                                    }
                                }
			   }
                       })
                    }
                    If ((Local1 == 0x02)){}
                    If ((Local1 == 0x03)){}
                    If ((Local1 == 0x04)){}
                    If ((Local1 == 0x05))
                    {
                        If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
                        {
                            \_SB.PCI0.LPCB.EC0.S0IX (One)
                        }

                        If (CondRefOf (\_SB.MS0X))
                        {
                            \_SB.MS0X (One)
                        }

                        If (CondRefOf (\_SB.PCI0.EGPM))
                        {
                            \_SB.PCI0.EGPM ()
                        }
                    }

                    If ((Local1 == 0x06))
                    {
                        If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX))
                        {
                            \_SB.PCI0.LPCB.EC0.S0IX (Zero)
                        }

                        If (CondRefOf (\_SB.MS0X))
                        {
                            \_SB.MS0X (Zero)
                        }

                        If (CondRefOf (\_SB.PCI0.RGPM))
                        {
                            \_SB.PCI0.RGPM ()
                        }
                    }

                    Return (Buffer (One)
                    {
                         0x00
                    })
                }

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 19:39:42 +00:00
Tim Wawrzynczak d96f3a25b4 acpigen: Add ability to auto-generate _DSM Function 0
Since the value returned by _DSM function 0 for a given UUID is trivial
to calculate, add the ability to do so to the
acpigen_write_dsm() functions.

Change-Id: Id9be050442485b42202cf91649aa94e56f35032a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 19:39:09 +00:00
Tim Wawrzynczak e2b8f30bee soc/intel/alderlake: Set LpmStateEnableMask UPD
Use the get_supported_lpm_states() function to set the respective FSP
UPD.

TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 19:38:46 +00:00
Tim Wawrzynczak 6cf79d9d14 soc/intel/alderlake: Add get_adl_cpu_type function
This function searches the known MCH device IDs for Alder Lake and
returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or
unknown.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10 19:36:07 +00:00
Hung-Te Lin 1fc92dee52 mb/google/asurada: enable MIPI_DSI_MODE_LINE_END to fix display issues
The ANX7625 needs explicit LINE_END to output proper
display data.

This patch is based on CB:51435 (commit b923931,
"mb/google/kukui: Add flag for MIPI_DSI_MODE_LINE_END ANX7625")

BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada

Change-Id: Id5666fa1bcf96002725509d7436ea1ff5febef93
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57486
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 13:24:24 +00:00
Hung-Te Lin 5e8af51d1e mb/google/asurada: power on panel after DSI is ready
Some bridge chips or panels require DSI signal output
before the DSI receiver is ready to work.

This patch is based on CB:47380 (commit b32e4d6,
"mb/google/kukui: Add panel api after dsi start")

BUG=b:198558237
TEST=emerge-asurada coreboot
BRANCH=asurada

Change-Id: Id72560caee9352f88db2de7269b1472f56ac1bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10 13:24:10 +00:00
Julius Werner 8202fc42d4 util/cbmem: Add -2/--2ndtolast option to print second-to-last boot log
On some platforms, runtime firmware crashes write logs to the CBMEM
console. For those, since a crash reboots the system, by the time we
have a chance to run `cbmem` again the boot where the crash happened
will be the one before the "last" (current) boot. So cbmem -1 doesn't
show the interesting part, and cbmem -c potentially shows a lot that is
cumbersome to dig through. This patch introduces a new option cbmem -2
to explicitly show only the boot cycle before the last one.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6725698f4c9ae07011cbacf0928544cebb4ad6f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-09-09 23:05:03 +00:00
Karthikeyan Ramasubramanian 2c59a3884d Revert "soc/amd/common: Skip psp_verstage on S0i3 resume"
This reverts commit b90e6fdd25. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.

BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09 20:41:31 +00:00
Kevin Chiu 36aab93072 mb/google/guybrush/var/nipperkin: Add ELAN TS support
ELAN TS: eKT3644

BUG=b:194961444
TEST=emerge-guybrush coreboot chromeos-bootimage
     TS is functional

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id1601efbbe419bb28233a2678fdde005a55da671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 20:41:20 +00:00
Stanley Wu 5140dd263b mb/google/dedede/var/gooey: Add fw_config probe for ALC5682-VD & VS
ALC5682-VD/ALC5682-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.

ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"

BUG=b:193694180
TEST=ALC5682-VD/ALC5682-VS audio codec can work

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Ib458cf47909a2d7a65f086c5f30f85a16f78d589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-09 20:40:37 +00:00
Felix Held f4e6466924 soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.

BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09 17:49:48 +00:00