Commit Graph

180 Commits

Author SHA1 Message Date
Julius Werner 98eeb96135 commonlib: Add commonlib/bsd
This patch creates a new commonlib/bsd subdirectory with a similar
purpose to the existing commonlib, with the difference that all files
under this subdirectory shall be licensed under the BSD-3-Clause license
(or compatible permissive license). The goal is to allow more code to be
shared with libpayload in the future.

Initially, I'm going to move a few files there that have already been
BSD-licensed in the existing commonlib. I am also exracting most
contents of the often-needed <commonlib/helpers.h> as long as they have
either been written by me (and are hereby relicensed) or have an
existing equivalent in BSD-licensed libpayload code. I am also
relicensing <commonlib/compression.h> (written by me) and
<commonlib/compiler.h> (same stuff exists in libpayload).

Finally, I am extracting the cb_err error code definitions from
<types.h> into a new BSD-licensed header so that future commonlib/bsd
code can build upon a common set of error values. I am making the
assumption here that the enum constants and the half-sentence fragments
of documentation next to them by themselves do not meet the threshold of
copyrightability.

Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-28 06:36:13 +00:00
Johanna Schander 4ddbbd84d9 util/inteltool: Add MCHBAR dumping support for Ice Lake U systems
According to intels datasheet

Document Number: 341078-001
10th Generation Intel® Core™ Processor Families
Volume 2 of 2

we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs.
The difference is that on ICL the MCHBAR address is definited by
the bits 38:16 instead of 38:15 giving the constraint that it has
to be 64kbit instead of 32kbit aligned. (Section 3.1.13)

Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-10 15:14:02 +00:00
Johanna Schander d756c27a54 util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christoph Pomaska <github@aufmachen.jetzt>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-29 21:13:17 +00:00
Felix Singer 19e353473d inteltool: Add method 'print_system_info'
To get a better idea what this code does, this patch adds
a new method called 'print_system_info'.

Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28 12:00:46 +00:00
Maxim Polyakov 9af10bf90f util/inteltool: Add server 5065x CPU model support
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).

The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.

These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
    Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
    Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
2019-10-22 12:56:20 +00:00
Maxim Polyakov 4fb80753f5 util/inteltool: remove unsupported MSRs for 06_9EH
Change-Id: I5c1e4d20efa7630bf4e6210591790055ead0161c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:56:23 +00:00
Maxim Polyakov 9ebf5317bc util/inteltool: fix 6d0H-6dfH MSR names for 06_9EH
Change-Id: I92e8f5194114f7756e3858ff13c207daebe8167c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:53:35 +00:00
Maxim Polyakov 3e7ff29995 util/inteltool/cpu: fix IA32_PLATFORM_ID MSR addr
According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.

[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
    Manual. Volume 4: Model-Specific Registers. May 2019.
    Order Number: 335592-070US

Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:42:47 +00:00
Maxim Polyakov 43a98b9589 util/inteltool: remove duplicate MSR for 06_9EH
Change-Id: I34981a69ad027444bc757449db2366f51c13f0e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-12 11:40:58 +00:00
Sellerie 409a5dc8af util/inteltool: Add Intel HD 4400 (Haswell IGD)
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.

It is found on the ark page of e.g. the Intel i3-4130 CPU.

Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 17:18:22 +00:00
Maxim Polyakov 1317689066 inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O

Change-Id: I4b429536fc2db16d770120487e4c383da437593a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 15:00:04 +00:00
Maxim Polyakov b89ce2e1b4 inteltool: add Lewisburg C62x GPIOs support
These changes are in accordance with the documentation:
[*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass

Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 14:59:09 +00:00
Maxim Polyakov ec32e61bb8 inteltool: add Lewisburg family C62x chipset PCI IDs
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-04 08:16:04 +00:00
Felix Singer f98dc48386 inteltool: Add GPIO support for Skylake-H chipsets
PCH IDs:
  - H170, Z170, Q170, Q150, C232, QM170, HM170

Used documents:
  - Intel 332690-005EN

Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31 18:06:07 +00:00
Pavel Sayekat 9429b70f91 util/inteltool: Add H110 GPIO support
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 18:06:13 +00:00
Jacob Garber 52f0e84ba7 util/*/Makefile: Rename -W to -Wextra
-W is the old name for -Wextra, so let's rename it to be consistent with
the rest of the utility Makefiles.

Change-Id: I0e50f13d2617b785d343707fc895516574164562
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-23 09:10:47 +00:00
Jacob Garber 198c2e63ac util/inteltool: Shrink buffer size
512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.

Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-16 16:25:11 +00:00
Jacob Garber 57f2188d86 util/inteltool: Enable -Wmissing-prototypes
Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:23:55 +00:00
Jacob Garber 6faccd1f00 util/inteltool: Make internal functions static
None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:23:42 +00:00
Christian Walter 9a8c5e7ac0 util/inteltool: Add Kabylake E3-1200 Support
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15 17:21:39 +00:00
Jacob Garber a75440739d util/inteltool: Use appropriate channel for printing timings
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:24:14 +00:00
Felix Singer 0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:38:49 +00:00
Jacob Garber 94d61ecab0 util/inteltool: Swap conditions to prevent uninit reads
Both values in each array are only initialized if
`two_channels` is true, so we need to check that first.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:27:11 +00:00
Thomas Heijligen 725369fd0c inteltool: add 300 and C240 Series PCH
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h

On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.

Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-15 12:58:28 +00:00
Felix Singer 24b000a160 inteltool: Add multiple device IDs of Intel GPUs
* Intel HD Graphics 510
* Intel HD Graphics 515
* Intel HD Graphics 520
* Intel HD Graphics 530 (2x)
* Intel UHD Graphics 615 (2x)
* Intel UHD Graphics 617
* Intel UHD Graphics 620 (3x)
* Intel UHD Graphics 630 (7x)
* Intel UHD Graphics 640
* Intel Iris Graphics 540
* Intel Iris Graphics 550
* Intel Iris Pro Graphics 580
* Intel Iris Plus Graphics 650
* Intel Iris Plus Graphics 655

Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 11:29:51 +00:00
Nico Huber 8a95c6c48d util/inteltool: Add Apollo Lake GPIO groups and names
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.

Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.

Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)

Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05 11:56:02 +00:00
Thomas Heijligen da02719462 util/inteltool: Add support for Denverton
Used documents:
- C3000 Product Family Datasheet

Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae
Co-authored-by: Felix Singer <migy@darmstadt.ccc.de>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/30887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-21 13:27:24 +00:00
Shaleen Jain 2822d66238 util/inteltool: fix PCR init of Sunrise Point-LP devices
Fixes getting a dump of GPIO registers for these devices.

Change-Id: I80f05a170152969ba45d6aee33ab7ed5296ee496
Signed-off-by: Shaleen Jain <shaleen@jain.sh>
Reviewed-on: https://review.coreboot.org/c/30604
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-05 11:15:04 +00:00
Matthew Garrett 2bf28e52ee util/inteltool: Add support for Sunrise Point LP
Used documents:
334658 (Sunrise Point-LP I/O datasheet vol. 1)
334659 (Sunrise Point-LP I/O datasheet vol. 2)
332690 (Sunrise Point I/O datasheet vol. 1)

Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/28623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-28 22:31:54 +00:00
Nico Huber 94473afcd2 util/inteltool: Add Apollo Lake LPC ID and allow to read PCRs
The P2SB (PCI to Side-Band) bridge is on a different PCI device on APL.
Hence, we have to decide based on the LPC ID which device to query.

Also fix a comment.

Change-Id: Ie20d7d2d246629d085bcf4740ba28b1e81e6a12a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-29 21:03:24 +00:00
Yegor Timoshenko c2e4941367 treewide: use /usr/bin/env where appropriate
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.

Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-17 07:32:03 +00:00
Fehér Roland Ádám d5a8155f1b util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.

Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18 19:42:11 +00:00
Tom Hiller 8ba9e8cf63 util: Add description.md to each util
Descriptions are taken from the files themselves or READMEs. Description
followed by a space with the language in marked up as code.

Change-Id: I5f91e85d1034736289aedf27de00df00db3ff19c
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-26 13:26:50 +00:00
qeed b775a62bb9 inteltool: Add PCI IDs for the C220 PCH series
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.

Intel Document 328904 is the datasheet for this PCH.

Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-21 17:39:48 +00:00
Youness Alaoui d8214d7e0e inteltool: Add dumping of full PCR ports
SoCs from Skylake on have many settings as so called private con-
figuration registers (PCRs). These are organized as 256 ports with
a 64KiB space each. We use the Primary to Sideband (P2SB) bridge's
BAR to access them.

Change-Id: Iede4ac601355e2be377bc986d62d20098980ec35
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19593
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11 20:55:06 +00:00
Elyes HAOUAS dfe8d64459 util/inteltool: Add Pentium 4 model f6x
Tested on Pentium 4, CPUID = 0F65 board: NEC 945G-M4.

Change-Id: I27c4bb0aed3259aa332581384077e000c9fb4b4c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04 02:31:51 +00:00
Nico Huber 54fe32f677 inteltool: Add some Skylake desktop ids
Change-Id: I1738a2544eb2435cb4b8718bcce5170d1ef04f72
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-27 15:42:14 +00:00
Nico Huber d91c932517 util/inteltool: Add missing #include <string.h>
Change-Id: I7bb142d9f936b73e84d301028069d85cc15d596a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/25143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-03-15 08:49:49 +00:00
Arthur Heymans 485c0ad078 inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI
Tested to display the register content correctly on a Lenovo Thinkpad
X220.

Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-02-06 16:11:45 +00:00
Arthur Heymans 921fa84f9e inteltool: Fix displaying 64bit spi registers
The registers were taken from the wrong addess since the spibar offset
was not added to it.

This also fixes the endianness.

Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06 16:09:03 +00:00
Nico Huber 1898023fb1 inteltool: Dump Sunrise Point PCH-H GPIO groups
Change-Id: Ib6b083c31617e19cbbb0929e2fc8ab39d54533bf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15 01:18:36 +00:00
Nico Huber 99b02a1d7c inteltool: Support for nasty Primary to Sideband Bridge (P2SB)
The Primary to Sideband Bridge (P2SB) is the interface to Private Con-
figuration Registers (PCR) including GPIO configuration. Of course,
access is restricted to Intel partners and criminals, so the PCI device
is hidden from the OS. Probably we only need to fetch the SBREG_BAR
address and can hide the PCI device again after that.

Change-Id: Ic121a09f021708aab82ae4b9d76d6c3c6fb884fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-15 01:18:05 +00:00
Christoph Pomaska 48ac29ee4c util/inteltool: Add Skylake Desktop Northbridge
Add the 8086:191f North/Host Bridge to the list of definitions.
Adding the definiton makes the Northbridge get recognized by inteltool.

It is found in the Intel i5-6600K CPU:
https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz

Change-Id: Id746d1e8b3bb90b3b68a2f6c372890671dd61b5f
Signed-off-by: Christoph Pomaska <cp_public@gmx.de>
Reviewed-on: https://review.coreboot.org/23055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-01-10 22:04:33 +00:00
Paul Menzel ceac787a4f inteltool: Add hint for compiler to avoid fall-through warning
Falling through is intended here, so add a comment that GCC will notice
and stop warning about this.

Change-Id: I12637b6bc18844a3bc47f06208df7fee7a4feb3b
Found-by: gcc-7 (Debian 7-20170316-1) 7.0.1 20170316 (experimental) [trunk revision 246203]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Omar Pakker
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-12-22 16:54:16 +00:00
Patrick Rudolph 2d26a36910 util/inteltool: Add GPU device IDs
Add PCI device IDs for several Intel GPUs.

Change-Id: I7d6ba16b2b115187fd57a31716f23a610b520d3e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-12-20 16:41:46 +00:00
Maximilian Schander ae848f8719 util/inteltool: Add Skylake definition to MCHBAR reading
Taken from
   * 6th Generation Intel Processor Families for S-Platform 
       Volume 2 of 2
   * Page 56
   * 332688-003EN

Change-Id: I46c8dd77823870b55cc040f7f6c557cb5a2562a1
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:45 +00:00
Maximilian Schander 798564333d util/inteltool: Add PCIEXBAR and PXPEPBAR reading for Skylake
Both registers behave the same as on the previous generation

Taken from
 * 6th Generation Intel Processor Families for S-Platform
     Volume 2 of 2
 * Page 55 and 62
 * 332688-003EN

Change-Id: Id02a38a7ab51003c9d0f16ebb2300a16b66a15f9
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:26 +00:00
Maximilian Schander 98c11ddc9e util/inteltool: Add Skylake DMIBAR register dumping
Register definitions were taken from
 * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2
 * Page 117
 * 332688-003EN
As well as
 * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2
 * Page 117
 * 332987-002EN

Tested on a 6th gen skylake mobile cpu and capability registers do match up
with the default values.

Change-Id: I636f6c3d045e297f1439d3e88e43f41e03db4c8e
Signed-off-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/22345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-08 11:42:20 +00:00
Maximilian Schander cb2d21d24d inteltool: Add southbridge and CPU definitions for Skylake
Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d
Signed-off-by: Maximilian Schander <maxschander@googlemail.com>
Reviewed-on: https://review.coreboot.org/22211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-03 16:18:53 +00:00
Maciej Suminski d5fb99eab6 util/inteltool: Remove duplicated error message, switch to snprintf
Passing a string containing output from strerror() to perror() causes
double error message display. It is also causing segfaults when the
error message is longer than temp_string capacity.

To fix the problems, sterror() call has been removed so the error
message is printed only once. This could be enough to avoid segfaults,
but it is a good practice to limit output size with snprintf().

Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce
Signed-off-by: Maciej Suminski <maciej.suminski@cern.ch>
Reviewed-on: https://review.coreboot.org/21025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-22 10:10:34 +00:00