Commit Graph

658 Commits

Author SHA1 Message Date
Martin Roth 2cee2ff256 Documentation: Add documentation on jenkins builders
Put this in a new directory called 'infrastructure' and make a link
and an index.md file for the directory.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25 08:56:27 +00:00
Angel Pons 0ec903a73b Doc/mb/lenovo/Sandy_Bridge_series.md: Clarify installation
Unlike Ivy Bridge series, there isn't a method to flash coreboot
internally when running vendor firmware (yet). Until someone finds a way
to bypass flash protections, the first flash has to be done externally.

Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24 23:21:23 +00:00
Angel Pons 76943a3443 Doc/mb/lenovo: Correct typo
Change-Id: If31c59f21c5533d8b5b015c9e60edd6e4e7072e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 23:21:17 +00:00
Michael Niewöhner d509ee55b6 soc/intel/apl: drop LPC pad configuration code
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.

Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 09:23:23 +00:00
Patrick Rudolph 6279cabb5b Documentation: Fix toctree and remove dead links
Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:36 +00:00
Patrick Rudolph fc1d50a365 Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.

The bugs are so strange that no root cause could be found yet.

Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:30 +00:00
Sam Lewis 1c18f8679f Documentation: Add Beaglebone Black documentation
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24 08:30:28 +00:00
Angel Pons 9223b71a4c Doc/mb/lenovo: Explain simpler GM45 flash method first
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.

Also, reword a sentence on the simple flashing procedure for clarity.

Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:33 +00:00
Angel Pons d0fd7b0693 Doc/mainboard: Sort Lenovo laptop generation groups
GM45 is older than Arrandale, so swap their order.

Change-Id: I5b94d940c0378dd561535257d3352700fd482527
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:27 +00:00
Furquan Shaikh 339269d587 Docs/cbfstool: Add details about memory mapped window handling
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.

BUG=b:171534504

Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-11 01:11:16 +00:00
Jonathan Zhang 36854a831e Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has
reached EVT exit parity. Update the documentation accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-05 09:47:00 +00:00
Michael Niewöhner 43dd2e458f docs/mb/supermicro/x11-lga-series: Update documentation
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726
- Add missing reference to X11SSH-F
- Drop TODO reference; there are no TODOs left

Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 20:49:16 +00:00
Michael Niewöhner 4c56d79ba6 {docs/,}mb/supermicro/x11ssh-tf: drop TODO section
Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.

Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:49:04 +00:00
Michael Niewöhner ce04a42db9 docs/mb/supermicro/x11ssm-f: Update board documentation
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
  function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
  whole paragraph. Also add a note about flashing via the BMC web
  interface.

Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:48:55 +00:00
Paul Menzel 9226fe9aee Documentation: Mention newer Intel μ-code updates in 4.13 release notes
Start a new section *Notes* for these kind of information.

Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:21:29 +00:00
Angel Pons c930c87998 Doc/releases/checklist.md: Fix up URLs
Use angle brackets so that they appear as links, and update a link to a
Gerrit change to use the current format.

Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:58 +00:00
Angel Pons 5ea7bb74bd Doc/releases/checklist.md: Add reminder to unpack relnotes
Explicitly add this easy-to-forget step. Also add a missing period.

Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:48 +00:00
Maxim Polyakov 0fcd37172f mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.

Working:
  - UART console and I2C on Kontron kempld;
  - USB2/3
  - Ethernet controller
  - eMMC
  - SATA
  - PCIe ports
  - IGD/DP
  - SMBus
  - HWM

Not tested:
  - IGD/LVDS
  - SDIO

TODO:
  - HDA (codec IDT 92HD73C1X5, currently disabled)

Tested payloads:
  - SeaBIOS
  - Tianocore, UEFIPayload - without video, EFI-shell in console only

Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)

Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22 22:18:22 +00:00
Angel Pons 5c186c6777 Documentation/releases: Update for 4.13
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.

Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 12:01:35 +00:00
Felix Singer d959a20114 mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3

WIP:
- Documentation

Not working:
- EC ACPI (e.g. Fn keys, battery and power information)

Boots Arch Linux (Linux 5.8.12) successfully.

Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20 11:57:11 +00:00
Angel Pons 27f606b721 doc/relnotes/4.13: Remove duplicated `CPU`
Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 17:13:22 +00:00
Nico Huber 2421b88381 doc/relnotes/4.13: Fix random spelling mistakes
Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:32:13 +00:00
Furquan Shaikh a8e7b45816 Doc/relnotes/4.13: Add details about resource allocator v4
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.

Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 16:23:46 +00:00
Nico Huber 900c3a32a3 doc/relnotes/4.13: Add changes to log-level configurability
Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:22:23 +00:00
Felix Singer 1268d4081e doc/relnotes/4.13: Add note about PCI bus mastering Kconfig options
Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 13:23:30 +00:00
Angel Pons 9fe0615ecc Doc/relnotes/4.13: Add several relevant changes
While some of these have little impact, they are worth mentioning here.

Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-13 16:11:48 +00:00
Julius Werner 9c50462fd7 Delete mainboard/google/cheza
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-12 01:43:09 +00:00
Harshit Sharma 678e401eb8 Documentation/releases: Add ASan to 4.13 relnotes
Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-11 10:28:05 +00:00
Iru Cai 85d0e7611a mb/hp: Add HP EliteBook Folio 9480m
The code is based on autoport, with necessary modifications.

This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.

Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.

Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-10 06:16:05 +00:00
Iru Cai 136380fcac Documentation: Introduce HP Sure Start and the method to bypass it
Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:38:32 +00:00
Matt DeVillier 12d515dcc5 mb/purism/librem_cnl: Add new variant 'Librem Mini v2'
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.

Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:48:23 +00:00
Matt DeVillier 184c794086 docs/librem_mini: update CPU, known issues section
Both 8565U and 8665U CPUs are used in the Librem Mini.

SATA issue updated based on addition of HSIO PHY tuning params
and resulting changes.

Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31 21:46:06 +00:00
Tim Wawrzynczak 24b4af668b fw_config: Convert fw_config to a 64-bit field
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.

BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:24:52 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Bill XIE 14ee0f94f3 mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20 09:00:18 +00:00
Paul Menzel b9a5152cfa Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:59 +00:00
Duncan Laurie 2cc126be2c drivers/intel/usb4: Add driver for USB4 retimer device
The USB4 retimer device needs to declare a _DSM with specific functions
that allow for GPIO control to turn off the power when an external
device is not connected.  This driver allows the mainboard to provide
the GPIO that is connected to the power control.

BUG=b:156957424

Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:51:40 +00:00
Iru Cai 871f62c376 lenovo/t440p: Add HDA verbs from the OEM firmware
To get the HDA verbs from the OEM firmware, open the firmware with
UEFITool, search for the existing HDA verbs, extract the UEFI module
and look for the verbs. Copy the consecutive 4 dword sets that look
like HDA verbs.

It is tested to make audio output from both the speaker and headphone
work.

Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:48 +00:00
Jonathan Zhang 339fa7389b doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:37:57 +00:00
Christian Walter 90b0d85e73 Documentation/mainboard: Add Missing OCP Delta Lake Link
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:32:50 +00:00
Elyes HAOUAS 3f56b87c51 Documentation/getting_started/kconfig.md: Add a note about Kconfig defaults
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.

Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25 08:41:45 +00:00
Harshit Sharma d8a722cb61 Documentation: Add ASan documentation
Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21 07:45:37 +00:00
Bob Moragues c06c0ce559 strongbad / coachz : Add Initial Support
BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 22:32:34 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Patrick Georgi 4ad85ed156 Documentation: Discuss how we use language
Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31 20:23:22 +00:00
Patrick Rudolph e828663392 Documentation: Update release notes for x86_64
Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31 17:08:58 +00:00
Angel Pons 85a4463976 Doc/soc/intel: Add info about microcode updates
Document a general overview of when and how microcode should be updated.
Also explain what microcode updates are, and why they are required.

Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26 07:36:12 +00:00
Matt DeVillier dff9994b96 docs/purism/librem_mini: Fixup CPU model, markup links
Change-Id: I26c0936c912490fc0ba28ee53139e3a1f3a00911
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-21 18:17:17 +00:00
Patrick Rudolph 57907fcebf mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes

Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM

Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19 10:50:49 +00:00
Patrick Rudolph e563815e05 arch/x86/boot: Jump to payload in protected mode
*   On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
*   Add a helper function to jump to arbitrary code in protected mode,
    similar to the real mode call handler.
*   Doesn't affect existing x86_32 code.
*   Add a macro to cast pointer to uint32_t that dies if it would overflow
    on conversion

Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-19 09:06:43 +00:00
Sam Lewis cb287987a1 arch/arm: Enable FIT payloads
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.

TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.

Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-19 07:16:59 +00:00
Matt DeVillier 87093758c5 documentation: Add documentation for Purism Librem Mini
Change-Id: Ie5699942f48d2d5b1417f447a9a36b98e4b18156
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 16:01:05 +00:00
Iru Cai 1bda1c356a mainboard: Add HP EliteBook 2560p
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.

Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:25:19 +00:00
Rocky Phagura afb7a81478 cpu/x86/smm: Introduce SMM module loader version 2
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores).
Current coreboot SMM is unable to handle more than ~32 CPU threads.
This patch introduces a version 2 of the SMM module loader which
addresses this problem. Having two versions of the SMM module loader
prevents any issues to current projects. Future Xeon-SP products will
be using this version of the SMM loader.  Subsequent patches will
enable board specific functionality for Xeon-SP.

The reason for moving to version 2 is the state save area begins to
encroach upon the SMI handling code when more than 32 CPU threads are
in the system. This can cause system hangs, reboots, etc. The second
change is related to staggered entry points with simple near jumps. In
the current loader, near jumps will not work because the CPU is jumping
within the same code segment. In version 2, "far" address jumps are
necessary therefore protected mode must be enabled first. The SMM
layout and how the CPUs are staggered are documented in the code.

By making the modifications above, this allows the smm module loader to
expand easily as more CPU threads are added.

TEST=build for Tiogapass platform under OCP mainboard. Enable the
following in Kconfig.
        select CPU_INTEL_COMMON_SMM
        select SOC_INTEL_COMMON_BLOCK_SMM
        select SMM_TSEG
        select HAVE_SMI_HANDLER
        select ACPI_INTEL_HARDWARE_SLEEP_VALUES

Debug console will show all 36 cores relocated. Further tested by
generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all
cores entering and exiting SMM properly. In addition, booted to Linux
5.4 kernel and observed no issues during mp init.

Change-Id: I00a23a5f2a46110536c344254868390dbb71854c
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15 02:16:32 +00:00
Patrick Rudolph 8daa12f7e0 arch/x86/postcar: Add x86_64 support
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.

Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14 17:55:26 +00:00
Jonathan Zhang 6e36ee2544 doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release
cycle.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14 09:07:32 +00:00
Balazs Vinarz ffa710b9dd mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 17:34:04 +00:00
Patrick Georgi 20245aa622 Documentation: Fix sphinx configuration
Without the brackets, the string seems to be added as a list of
characters, and since there's no extension called 's', sphinx
bails out.

Change-Id: If0fc9c1a74f334b6154df3cb26836509de913567
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44114
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04 12:18:29 +00:00
Paul Menzel e1574e31f6 Doc/mb/facebook/monolith: Correct grammar by removing plural *s*
Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:09:50 +00:00
Paul Menzel d3d316a28f Doc/mb/lenovo: Mark up file name as code/monospace
Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:08:58 +00:00
Jonathan Zhang b84bd303ee doc/getting_started: update name of file generated by "make savedefconfig"
Update kconfig.md to reflect that defconfig (instead of mini-config)
file is generated by running "make savedefconfig".

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:36:33 +00:00
Patrick Georgi 71a22e3cfc Documentation: Revise "24 hours wait period" rules
They're more or less the same but reworked for hopefully some more
clarity. There have been some best practices around documenting the
reason for expedited processing so let's make them official, too.

Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 09:18:26 +00:00
Paul Menzel 229616419d Doc/mb/facebook/monolith: Use correct TianoCore commit hash
The commit hash is the same as the SeaBIOS one, and is indeed from the
SeaBIOS repository.

Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:24:05 +00:00
Rizwan Qureshi ec321094f6 soc/intel/common/basecode: Implement CSE update flow
The following changes are done in this patch:
 1. Get the CSE partition info containing version of CSE RW using
    GET_BOOT_PARTITION_INFO HECI command
 2. Get the me_rw.version from the currently selected RW slot.
 3. If the versions from the above 2 locations don't match start the update
    - If CSE's current boot partition is not RO, then
        * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
          HECI command.
        * Send global reset command to reset the system.
    - Enable HMRFPO (Host ME Region Flash Protection Override) operation
      mode using HMRFPO_ENABLE HECI command
    - Erase and Copy the CBFS CSE RW to CSE RW partition
    - Set the CSE's next boot partition to RW using
      SET_BOOT_PARTITION HECI command
    - Trigger global reset
    - The system should boot with the updated CSE RW partition.

TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995

Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:42:06 +00:00
Maxim Polyakov a76a64833b soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
2020-07-26 21:33:08 +00:00
David Hendricks 4cdc698707 Doc/tutorial/part1.md: Show how to list toolchain targets
Change-Id: I276ea0a6b52b55b8772c76f48f7a0fb149af6e78
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 04:56:25 +00:00
Tim Wawrzynczak 0115ba8835 Documentation: Add documentation for drivers/intel/dptf chip driver
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-18 16:05:43 +00:00
Patrick Georgi b8d0d089b3 Documentation: Remove mention of manual checkpatch.pl invocation
We typically call checkpatch.pl through make lint which properly adds
the option to tell checkpatch that our lines may be 96 columns long.

However there's one mention of calling checkpatch directly and that
confuses people with complaints about overly long lines that exceed
80 columns.

The lint test that runs checkpatch (and with the right options)
can also be used on a per-directory basis, so offer that instead.

Change-Id: If21e925d2d2394c876724a44b0e23c9b2744c56b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-16 10:48:18 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Jonathan Zhang 34cfeee406 doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:44 +00:00
Patrick Rudolph f664321508 Documentation: Add several fixes
* Add support for Sphinx 3.0+
* Add backward support for Sphinx 1.8 and older
* Make sphinxcontrib ditaa an optional extension
* Allow SPHINXOPTS to be set from command line
* Add sphinx and sphinx-lint to top level Makefile

Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41492
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 21:51:26 +00:00
Kyösti Mälkki 239abaf759 ACPI GNVS: Replace uses of smm_get_gnvs()
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 05:14:24 +00:00
Angel Pons 05ba1e9bf2 Doc/mb/google/dragonegg: Drop abandoned project info
Commit 0013623 (mb/google/dragonegg: remove abandoned project) dropped
this mainboard because it is no longer in development nor used. However,
the associated documentation remained. Rest in pieces, Dragonegg. ;-;

Change-Id: Idd2ee716717132ba3fa237ae97f34686007d3685
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 09:19:52 +00:00
Bill XIE d87277abbf mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini PCIe
    - No docking
    - No TPM

Tested:
    - CPU i5-3337U
    - 8GiB SO-DIMM
    - Camera
    - PCIe and USB2 on M.2 slot with A key for WLAN
    - SATA and USB2 (no SuperSpeed components) on M.2 slot with B key for WWAN
    - On board SDHCI connected to PCIe
    - USB3 ports
    - libgfxinit-based graphics init
    - NVRAM options for North and South bridges
    - Sound
    - ThinkPad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from SeaBIOS.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29 15:51:23 +00:00
Jonathan Zhang c664b90f05 Doc/mb/ocp: Add documentation for Tioga Pass
Add OCP platform Tioga Pass documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If4c2832d5bd006c572dab035040b4242f8a3d53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 11:51:06 +00:00
Patrick Rudolph 2fdabd9038 smmstore: Verify userspace-provided pointer to protect SMM
Use the introduced functions and verify pointers in the SMMSTORE.
Make sure to not overwrite or leak data from SMM and update the
documentation as well.

Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:05 +00:00
Patrick Rudolph 41fec869fb cpu/x86/smm: Add helper functions to verify SMM access
* Add a function to check if a region overlaps with SMM.
* Add a function to check if a pointer points to SMM.
* Document functions in Documentation/security/smm

To be used to verify data accesses in SMM.

Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:17:56 +00:00
Furquan Shaikh 2778420f7f Documentation: Add section about SPD tools for TGL and JSL
CB:41612 added a new set of tools for generating SPDs for TGL and JSL
based mainboards. This change adds relevant documentation to
coreboot-4.13 release notes.

Change-Id: I168adad25df9195dec64e8104f2dbe992eebddc6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42092
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 18:39:15 +00:00
Kyösti Mälkki 4164476dfc mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:45:45 +00:00
Angel Pons 455097616c Doc/mb/gigabyte/ga-h61m-s2pv: Fix in-circuit programming
It is NOT supported. The board is not meant to be flashed externally.

Change-Id: If422810e84355cb94004e5ca2b95d239804699d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2020-06-06 20:13:34 +00:00
Christian Walter b646e28769 mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard.

Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.

Untested:
* CNVi
* Intel Graphics

Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS

Not Working:
* Intel HDA

Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-06 07:44:53 +00:00
Tim Wawrzynczak a4e2e0550c Documentation: Add section about 'hidden' devices to 4.13 release notes
CB:41384 (SHA dbcf7b1621) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.

Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06 01:33:38 +00:00
Duncan Laurie 36e6c6f8d2 fw_config: Add firmware configuration interface
This change introduces a new top-level interface for interacting with a
bitmask providing firmware configuration information.

This is motivated by Chromebook mainboards that need to support multiple
different configurations at runtime with the same BIOS.  In these
devices the Embedded Controller provides a bitmask that can be broken
down into different fields and each field can then be broken down into
different options.

The firmware configuration value could also be stored in CBFS and this
interface will look in CBFS first to allow the Embedded Controller value
to be overridden.

The firmware configuration interface is intended to easily integrate
into devicetree.cb and lead to less code duplication for new mainboards
that make use of this feature.

BUG=b:147462631
TEST=this provides a new interface that is tested in subsequent commits

Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02 16:40:04 +00:00
Jan Dabros 5694342a81 Documentation/tutorial: Add tutorial for writing unit tests
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I1ebd2786a49ec8bc25e209d67ecc4c94b475442d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-30 08:46:59 +00:00
Elyes HAOUAS a1b19de447 Documentation/acpi: Fix the path to variants/hatch/overridetree.cb
Change-Id: I7c3fd942318f28b4714bc7c2a47bedf85f7923ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 14:58:35 +00:00
Duncan Laurie ba56da85e8 Documentation: Add info about SoundWire coreboot implementation
This change adds a document about the SoundWire implementation in
coreboot with details adding new controllers and codecs and
connecting them in the mainboard devicetree.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibc04442e22acfc03ff86c49c8a7a215ceefc24c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40892
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22 01:49:11 +00:00
Bill XIE cfd78b1500 Revert "mainboard/lenovo/x230: Add ThinkPad x230s as a variant"
This reverts commit 6b95507ec5, in order
to recommit and review it again.

Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21 02:50:08 +00:00
Matt DeVillier dd467bfc14 drivers/intel/gma: Add override for presence straps
A handful of boards do not properly implement the presence straps,
leading libgfxinit to fail to detect an attached display. Add an
override, defaulting to N, which can be set for affected boards.

Add a section to the documentation detailing the option and its usage.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I43c61d67147878887658b23d90fb1c0b91e7a2af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-20 23:38:05 +00:00
Patrick Georgi 736024afdb Documentation: Encourage documentation with code changes
The resource allocator woes post-4.12 release showed room for
improvement on both discussion and documentation.  To encourage this
(and encourage reviewers to look out for issues in that space),
extend the review guidelines so that they encourage to more clearly
document the reason for a change with the change (commit message or
our documentation) and also to loop in the mailing list.

Change-Id: I1962dba3fe7e1a01fa4c8b0058297c7d050cb7b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20 08:44:26 +00:00
Raul E Rangel cbaa835f21 soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs
BUG=b:147042464
TEST=Boot trembyle to OS

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:40:51 +00:00
Patrick Georgi 33e19ac619 Documentation: Fix 4.12 release notes, improve checklist
Since I seem to forget to remove "Upcoming" in the release notes
every single time, and others might as well, fix it here and also
tell future release managers to take care of that.

Change-Id: I8ffe34f25e954621bdd635e115a8b1a914df9c27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:04:04 +00:00
Michał Żygowski 72f06ca554 mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support
Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:38:46 +00:00
Bill XIE 6b95507ec5 mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini pci-e
    - no docking
    - no tpm

Tested:
    - CPU i5-3337U
    - Slotted DIMM 8GiB
    - Camera
    - pci-e and usb2 on M.2 slot with A key for wlan
    - sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
    - On board SDHCI connected to pci-e
    - USB3 ports
    - libgfxinit-based graphic init
    - NVRAM options for North and South bridges
    - Sound
    - Thinkpad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from
      Seabios.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-13 12:10:38 +00:00
Angel Pons 56875113b7 Doc/mb/lenovo: Fix broken link
Change-Id: Iafa7e0f3734042e35e8b4ea440baf1c3c3d147e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-12 19:45:02 +00:00
Paul Menzel 3b3512941b Documentation/getting_started: Fix typo
Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12 19:41:43 +00:00
Patrick Georgi f2c32515ee Documentation/releases: Update for 4.12
Fill in some blanks for 4.12, mark it done, add template for 4.13.
Also update the list of vboot supported boards.

Change-Id: Id6b663f13367eb40e66af30aadd33991c8dd635c
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-12 10:30:22 +00:00
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Jan Dabros 50544a1999 Documentation/4.12-relnotes.md: Add a note about unit testing coreboot
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Id6365b86640832b91a722cd12f64c03fc8a41fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-11 13:36:31 +00:00
Patrick Georgi 2faeb11fcd treewide: more SPDX header work
Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-09 21:20:15 +00:00
Patrick Rudolph 0f4977705d Documentation: Update vboot on lenovo
Update the documentation now that CB:32705 is merged.

Change-Id: I9845c0750ec4016188478154610400d1b8556793
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40775
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04 19:17:54 +00:00
Furquan Shaikh 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5)
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 18:45:16 +00:00
Christian Walter e4c81bcca5 documentation: Add documentation ideas for season of docs
Let's gather some documentation ideas for the season of docs. I reused
the project ideas style (thanks Patrick). Feel free to add yourself as a
mentor here. Also if you have more ideas, please add them to the
document.

Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 13:47:06 +00:00
Evgeny Zinoviev d991bf1fb4 Doc/mb/51nb/x210: Do minor fixes
Fix code blocks, add a newline, use inline code blocks for commands.

Change-Id: Iecf04b00ed12323c124517f2557cc8b60640b618
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01 06:44:07 +00:00
Jan Dabros 6449b67427 Documentation: Add proposal for firmware unit testing
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I552d6c3373219978b8e5fd4304f993d920425431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-01 06:31:25 +00:00
Patrick Rudolph 8c82010c97 Documentation: Spell vboot all lowercase
Update all occurrences of vboot and spell it lowercase.

Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-28 06:14:25 +00:00
Patrick Rudolph fcfca1da5e Documentation: Add vboot on Lenovo devices
Describe vboot implementation details for retrofitted Lenovo ThinkPad devices.

Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39151
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27 08:52:52 +00:00
Jacob Garber 2246216971 Doc,util: Update list of utilities
Remove entries for old utilities and add entries for new ones.
Generated using util/util_readme, with some tweaks to preserve the
markdown.

Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20 06:55:49 +00:00
Iru Cai 7691ebc379 Doc/mb/hp: rename the document about HP laptops with KBC1126
Later EliteBooks use different EC chips and have different EC firmware
interfaces, so rename the document elitebook_series.md to a more
precise name and also do some rewriting.

A link to the code review page for 8760w is also added because the
port for this laptop is not merged yet.

Change-Id: I2f9b8c4e52ed760c16977d16838cca9e490cda05
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20 06:52:34 +00:00
Arthur Heymans 895c77f361 Documentation/vboot: Drop deprecated options from example
4K keys are now default.

Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:04:10 +00:00
Arthur Heymans 15161d9284 4.12 release notes: Add some explanation behind deprecations
Some features are made mandatory, meaning that some platforms have
been dropped from master. This also explains that further development
on these popular platforms can happen on the 4.11 branch.

TODO is this really the right place or is it too technical for release
notes?

Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-04-14 09:55:47 +00:00
dalao 56a25a98db mainboard/lenovo: Use the original hardware ids for keyboard/pointing
Currently coreboot is using the compatible ID PNP0303 for all keyboards
and PNP0F13 for all pointing devices, which causes some problems. On
Windows, the touchpad driver can't be automatically matched and
installed through Windows Update. On Linux, there are some strange
issues. So it's better to use the original hardware IDs for each model.
The hardware IDs for the following models can be found By searching for
dmesg logs on vendor BIOS:

T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html
Keyboard: PNP0303 Pointing: IBM0057

R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg
Keyboard: PNP0303 Pointing: IBM0057

X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out
Keyboard: PNP0303 Pointing: IBM3780

X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2
Keyboard: LEN0010 Pointing: IBM3780

T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log
Keyboard: LEN0010 Pointing: IBM3780

T510: https://bbs.archlinux.org/viewtopic.php?id=120287
Keyboard: PNP0303 Pointing: LEN0015

T410: https://forum.ubuntuusers.de/topic/kein-sound-109/
Keyboard: PNP0303 Pointing: LEN0015

T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T420s: https://bbs.archlinux.org/viewtopic.php?id=191510
Keyboard: PNP0303 Pointing: LEN0015

T520: https://bbs.archlinux.org/viewtopic.php?id=195636
Keyboard: PNP0303 Pointing: LEN0015

W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log
Keyboard: PNP0303 Pointing: LEN0015

T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU
Keyboard: LEN0071 Pointing: LEN0015

W530: https://bugs.freedesktop.org/attachment.cgi?id=115557
Keyboard: LEN0071 Pointing: LEN0015

L520: https://pastebin.com/U6MaBAY3
Keyboard: PNP0303 Pointing: LEN0017

X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1
Keyboard: PNP0303 Pointing: LEN0018

X220: https://bbs.archlinux.org/viewtopic.php?id=237669
Keyboard: PNP0303 Pointing: LEN0020

X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460
Keyboard: PNP0303 Pointing: LEN0020

X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg
Keyboard: MSF0001 Pointing: LEN0026

X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851
Keyboard: LEN0071 Pointing: LEN0030

s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt
Keyboard: PTL0001 Pointing: LEN0031

T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg
Keyboard: LEN0071 Pointing: LEN0034

X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg
Keyboard: LEN0071 Pointing: LEN0035

T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976
Keyboard: LEN0071 Pointing: LEN200e

Others:
https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c

Test result: This can make Windows automatically install the Lenovo
touchpad driver. It also fixes the T440p touchpad issue.

Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932
Signed-off-by: dalao <dalao@tutanota.com>
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:50:10 +00:00
Evgeny Zinoviev 408fdeba7f Doc/mb/lenovo/ivb_internal_flashing: Fix a typo
unmount -> umount. My mistake.

Change-Id: I5d1b675f6ab7c027f2e646424adb1f255967c753
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:44:21 +00:00
Christian Walter b2f8ce7591 soc/intel/cannonlake: Steal no memory for disabled IGD
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.

Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49

Tested on:
* CFL platform with IGD
* CFL platform without IGD

Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-09 21:49:01 +00:00
Nico Huber 04da5d72d9 fsp2_0: Clean up around `config FSP_USE_REPO`
We can make our lifes much easier by removing its dependency on
`ADD_FSP_BINARIES`. Instead, we imply the latter if the repository
is to be used. We can also hide a lot of unnecessary prompts in
this case.

Also, remove default overrides and selects for the two that are
now unnecessary.

Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05 23:26:04 +00:00
Angel Pons b54c5168bd Doc/mb/index.md: Fix mainboard vendor order
Oops, Libretrend "stole" all the Thinkpads from Lenovo. Correct that.

Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40118
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03 13:43:35 +00:00
Marcello Sylvester Bauer eff1306ea4 Documentation/mb/lenovo: Test shrunken ME on Ivy Bridge
Update the Lenovo Ivy Bridge documentation that no issues could be
observed on W530.

Tested on Lenovo W530 with stripped ME and found no issues:
commit 93b0c7cfc6

* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* mSATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* CPU temperature reporting
* Stress test stable (intel_pstate no_turbo due to W530 overheating bug)
  * Youtube videos
  * stress -c 8 -m 1 -t 3600

Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39603
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:32:25 +00:00
Patrick Rudolph 5271776689 Documentation: Add lemp9 to toctree
Fix "WARNING: document isn't included in any toctree" by adding
the lemp9 to mainboard/index.md.

Change-Id: Id6d8f9e2aab6dc7ad4baf1b37d88e531acb757f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25 16:10:15 +00:00
Christian Walter be3979c873 acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.

Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10

FWTS does not return FAIL anymore on ACPI tests

Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23 16:54:58 +00:00
Marcello Sylvester Bauer e9aef1fe45 Doc/security/vboot: Add a script generated device list
Add a script generated list of vboot enabled devices to the
documentation. Add a entry to the release checklist.

Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23 09:23:11 +00:00
Patrick Rudolph 903d9a225e Documentation: Add new GSoC projects
Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 14:44:47 +00:00
Matthew Garrett 2f62a352ea mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:

* EC firmware is contained within the system SPI flash, and so a blob of
  EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
  GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
  configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different

All hardware appears to work as expected, although the SD reader is
untested.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16 14:42:04 +00:00
Angel Pons 31b7ee4201 treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:

- Hillel:   32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics

This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.

Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:04:39 +00:00
Paul Menzel f897623aac mb/asus/p8z77-m_pro: Use uppercase for *PRO*
Consistently use the official uppercase spelling.

Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:00:07 +00:00
Paul Menzel fac491dab7 Docs: Fix link for ASUS P8Z77-M PRO
Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15 12:59:52 +00:00
Patrick Rudolph cb858d6d62 superio/nuvoton/nct5539d: Update documentation and remove DSDT
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.

Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 15:03:39 +00:00
Evgeny Zinoviev fc59f0860b Documentation: Fix a typo
filse -> files

Change-Id: Iaf0c3a064b42dde70b1e01cfc15ad3187bf8bfcc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-03-11 14:28:34 +00:00
Sebastian 'Swift Geek' Grzywna 49fb39b783 Documentation: Update codenames
austin-3 was a devel board, retracting
t60 comes in variants with discrete gpu and only intel gpu one

Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:26:32 +00:00
Michał Żygowski b9f9f6c12b mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:04:05 +00:00
Michał Żygowski 48be6b276a mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:03:17 +00:00
Michał Żygowski 83565dea86 mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 21:26:20 +00:00
Nico Huber 4ce52903b0 3rdparty/libgfxinit: Update submodule pointer
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.

  config GFX_GMA_PANEL_1_PORT
          default "DP3"

Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.

This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.

Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 08:20:12 +00:00
Evgeny Zinoviev ef613b97cf Documentation: Add Montevina ThinkPads common page
- Add a common page about Montevina ThinkPads.
- Describe how to disable ME and remove its firmware on these models.
- Describe vendor flash layouts.

Thanks to swiftgeek for his help when writing this, especially the last
paragraph and flash layouts.

Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:10:36 +00:00
Chris Morgan 5e5e789f9b nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge.  This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values.  Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.

Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-06 07:54:26 +00:00
Angel Pons 446e4dc238 util: Remove viatool
It somehow creeps into `make clean`, but is not used at all. Since no
VIA platform remains in coreboot, drop the utility as well.

Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04 15:46:44 +00:00
Rajat Jain 310623b2dd arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio
Add new helper function in the acpigen library, that use the underlying
soc routines.

Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:40:23 +00:00
Patrick Rudolph 4d9dd22bd1 Documentation: Add Heads to payloads
Add a small description about Heads.

Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 11:39:16 +00:00
Patrick Rudolph 0751d7bded Documentation: Add tutorial for me_cleaner on Lenovo devices
Add a tutorial how to use ME cleaner, and give some basic steps to
strip the ME. Update the Lenovo Sandy Bridge documentation that no
issues could be observed on X220 and give an example flash layout.

Tested on Lenovo X220 with stripped ME and found no issues:
commit: cbc5b99ac9

* Displayport
* VGA
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* Battery events
* CPU temperature reporting
* FAN managment
* Stress test stable
  * Youtube videos over Wifi
  * stress -c 2 -m 1 -d 1
  * glxgears

Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:39:05 +00:00
Arthur Heymans 4c28ccd0dc Docs/project_ideas.md: Add a memtest libpayload based payload
Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-28 10:42:57 +00:00
Patrick Georgi 6a4f46ac5e Documentation/project_ideas: Update after 2019
The coverity project is done, for the most part, so drop it. Expand
a bit on the scope of the toolchain binary project, and point out
that the Ghidra project already has code from GSoC 2019 but could be
developed further.

Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-24 14:20:04 +00:00
Elyes HAOUAS 2119d0ba43 treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:10:00 +00:00
Ivan Labáth 3ae1765df6 Documentation: getting_started/gpio.md: fix markup
Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d
Signed-off-by: Ivan Labáth <iger@labo.rs>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39082
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 12:59:53 +00:00
Evgeny Zinoviev 5efe122b27 Documentation: soc/amd/psp: Use real table markup
Currently, tables on this page are formatted as code blocks with
ASCII tables. Make it real beautiful tables.

Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:10:22 +00:00
Evgeny Zinoviev abe9673774 Documentation: Use inline code block for kernel parameter
Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:09:53 +00:00
Evgeny Zinoviev 286b07ca33 Documentation: Fix style issues on Lenovo X301 page
- Fix lists markup
- Some minor fixes in the text (e.g. lowercases)

Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-18 19:48:33 +00:00
Evgeny Zinoviev b3a247ccca Documentation: mb/lenovo: Make X1 uppercase
x1 -> X1.

Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:22:54 +00:00
Patrick Rudolph f6be41a988 Documentation/lenovo: Replace RST code with markdown
Latest Sphinx supports up path traversal in markdown. Replace old
RST code that's no longer needed to prevent it being copy and pasted.

Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:13:47 +00:00
Patrick Rudolph f9e10f26ba Documentation: Remove confusing xyz0 naming convention for Lenovo devices
Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge.
Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s.

Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:12:22 +00:00