Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.
TEST=build/boot google/drobit, verify able to boot from USB ports using
edk2 payload.
Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Inspect all type-C USB ports, check if there is a USB device attached,
and if so, send the connection request to the PMC. This allows for any
attached USB2/USB3 devices to be used for booting by the payload.
Since this functionality is only needed by ChromeOS devices with TCSS
running upstream coreboot, introduce a new Kconfig to guard its use.
Boards needing it will select it in subsequent commits.
TEST=tested with rest of patch train
Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable 'i' is unsigned, so use %zu vs %zd.
Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similarly to te_relocate(), on success pe_relocate() should return 0.
It has never been an issue so far as pe_relocate() return value is not
tested.
Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.
Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When lemp9 was converted to a variant in CB:64528, the Makefile was not
updated to handle the variant-specific `romstage.c`. This, as would be
expected, caused memory init errors and broke boot on CML-U boards.
Tested lemp9 boots to payload again.
Fixes: 5b7b04c938 ("mb/system76/cml-u: Convert lemp9 to a variant")
Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
BUG=b:279097356
TEST=On dibbi:
- flash OS 15449.0.0 (where suspend is broken due to b:274531972)
- run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28`
- check the AP wakes up immediately when the EC detects a sleep hang
Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.
BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
CPU TDP = 6 Watts, CPU PL4 = 60 Watts
Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
_DSD "StorageD3Enable" property is needs to be set under the root
port in the DSDT or SSDT. The ACPI _DSD method is the preferred way
to opt D3hot support for storage devices.
This also bypasses the low LTR from SSD that blocking S0i2.2
LTR/latency SoC requirement.
Name (_DSD, Package () {
ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
Package () {
Package (2) {"StorageD3Enable", 1},
// 1 - Enable; 0 - Disable
}
}
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were verified by the thermal team.
Based on thermal table in 290705146#comment11.
Set "tcc_offset" = "8"
BUG=b:290705146
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
To be consistent with other boards setting the keyboard backlight at
boot.
Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature was originally present and then dropped, but turns out
that users prefer it. Set the backlight to 50% in romstage, back to
zero in ramstage; skip enabling on the S3 resume path.
TEST=build/boot google/eve, verify keyboard backlight turns on/off
as expected.
Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the jack detect GpioInt resources under the codec (where they
belong), but also leave a copy under LPEA for since the Linux drivers
(incorrectly) require them there. Add pin list for Windows' SST driver.
Adapted from the Intel ValleyView edk2 ACPI reference code.
TEST=build/boot Win11, Linux on google/swanky; verify audio functional
OOTB under Linux, under Windows with coolstar's drivers.
Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
- add HRV and GpioIO for coolstar's windows drivers
- fix interrupt type for TI jack detect switch
TEST=build/boot Win11, Linux on google/cyan; verify audio working
OOTB under Linux, under Windows with coolstar's audio drivers.
Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Most of the components of this laptop are tested to work,
which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add packages required to extract the `mrc.bin` from a ChromeOS firmware
image as per the instructions provided in
https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html
Change-Id: I81ed4ef55f0ba745a8a0a0cc85c2b00360f59297
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67160
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The test for the docker cache directory was used by two different
targets, so turn it into its own target.
Add missing $ for whoami commands.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic5e1d28110097eb502959e81bafe77faa0fc7fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The coreboot-jenkins-test docker image takes the coreboot-jenkins-node
docker image and runs a series of tests to verify that things build
properly.
This was original created to test the coreboot-sdk, but build functions
like the documentation have been moved from the sdk image into the
jenkins node, so the test needs to be renamed.
Add the makefile target to the help and phony target list at the same
time.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0e6282bbb163064f177c8e68e7180ba2bdc101f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The JPEG decoder, that was added many years ago to display a boot-
splash in coreboot, has a few quirks. People used to do some voodoo
with GIMP to convert images to the right format, but we can also
achieve the same with ImageMagick's `convert`. The currently known
constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.
Beside that, we can only display the bootsplash if it completely
fits into the framebuffer. As the latter's size is often decided
at runtime, we can't do much more than offering an option to set
a specific size.
Change-Id: I564e0d89fb46503ff4c11e095726616700009968
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Include multiple hash tables into relevant CBFS.
BUG=b:277292697
TEST=Ensure that all multiple hash tables are part of Myst BIOS image
with PSP verstage enabled.
Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mainboards using Phoenix SoC with PSP verstage enabled, to
accommodate growing number of PSP binaries, multiple smaller hash tables
are introduced. Also some hash tables are in V2 format identifying the
concerned PSP binaries using UUID. Add SVC calls to support multiple
hash tables with different versions.
BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that
all the hash tables are injected successfully. Ensure that PSP validated
all the signed PSP binaries using the injected hash tables successfully.
Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently PSP verstage updates PSP bootloader with one unified hash
table containing hashes for all the signed PSP binaries to be validated.
With growing number of PSP binaries to validate and memory constraints
in PSP, there is a requirement to split and update the hash table into
multiple smaller chunks. Hence change the update_psp_fw_hash_table()
signature such that the hash tables are updated in a chipset specific
way.
BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the
Skyrim BIOS image and confirm that the hash table is identical before
and after this change.
Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some stages in bootflow prefer to use 16 bytes UUID instead of
traditional 2 bytes FWID to identify the firmware components they
verify/validate. Hence add version 2 of hash table which identifies
firmware components using UUID. Other than UUID and a reserved field for
alignment reasons, the format of the hash table is very similar to hash
table v1.
BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP Verstage enabled. Ensure that
the hash table v2 is built and installed into BIOS image for the
components that are configured in amdfw.cfg file. Ensure that the
validation by PSP is successful for all the relevant components during
the boot flow.
Change-Id: I2899154086cf8e90c3327178157b07ead034b16e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76586
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently this tool generates a hash table to verify signed binaries,
with a 2 byte FWID as the only kind of identifier. Going forward some
binaries are going to adopt 16 byte UUID identifiers and more binaries
will follow in the future SoCs. Hence add support for handling multiple
firmware identifier types. While at this remove the unused fwid from the
PSP FW table.
BUG=b:277292697
TEST=Build BIOS image and boot to OS in Myst & Skyrim.
Change-Id: I5180dc0fe812b174b1d40fea9f00a85d6ef00f2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby.
The wake issue either needs to be fixed, or S1 should not be advertised
as a capability in the ACPI table.
Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not
supported on Skyrim devices. This results in 'standby' being removed
from /sys/power/state.
BUG=b:263981434
TEST=suspend_stress_test
TEST=frostflow-rev2 ~ # cat /sys/power/state
freeze mem
Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since all indirect data fabric register accesses will be non-broadcast
accesses that target a specific data fabric instance, the
cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set
since that makes the indirect access target only a specific data fabric
instance.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.
This patch hooks up this parameter to devicetree.
BUG=b:286328295
TEST=Check code compiles & boot google/rex, and correct value has been
passed to FSP.
Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in
coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled.
This patch updates the Kconfig help text to meet PlatformDebugOption in
MTL and changes debug consent to 6 in default to provide basic SoC
debug capability.
TEST=Boot to OS on screebo and DBC connection is OK.
Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 9a7a677 from opensbi project moved the fu540 platform to generic
code and commit 26998f3 from opensbi removed the old non generic
platform. Therefore opensbi platform needs to change to generic.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tablet motion control is a function of the EC, and under Windows, the
TBMC device needs to be initialized after CREC, or driver init will
fail. The only way to ensure this happens is for TBMC to be a child
device under CREC.
TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers
loaded and orientation switching functional under both OSes.
Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
cse_prep_for_rw_update() should return CB_ERR when
cse_data_clear_request fails. It was modified to CB_SUCCESS in this
commit ad6d3128f8 ("soc/intel/common: Use enum cb_err values")
BRANCH=None
BUG=None
TEST=Verify the system goes to recovery during downgrade when
cse_data_clear_request() fails.
Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor
Lake SOCs. This config allows Intel FSP to programs TME engine to
generate a new key for each warm boot and exclude CBMEM region
from being encrypted by TME.
Bug=b:276120526
TEST= Boot up the system, generate kernel crash using following
commands:
$ echo 1 > /proc/sys/kernel/sysrq
$ echo "c" > /proc/sysrq-trigger
System performs warm boot automatically. Once it is booted,
execute following commands in linux console of the DUT and confirm
ramoops can be read.
$ cat /sys/fs/pstore/console-ramoops-0
S0ix also tested and found working.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Remove old workaround for automake and aclocal.
Change-Id: Ifc00a479fd08d9ee4d97df6da8762bae2d097827
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Matt DeVillier