Commit Graph

36944 Commits

Author SHA1 Message Date
Angel Pons 743159396a nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`
This changes the binary for the native raminit code path.

Tested on Asus P8Z77-V LX2, still boots with native raminit.

Change-Id: Ie8f1205a64e5264cb909d67c1dd402c18a6241ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:57:37 +00:00
Matt Papageorge ec0fb40893 Update amd_blobs submodule to upstream master
Updating from commit id 3bd9078:
2020-08-12 17:03:38 -0600 - (picasso: Update PSP to 0.8.6.7B)

to commit id e393a88:
2020-09-16 14:32:50 +0000 - (Update SMU firmware for Picasso, Pollock and Dali)

This brings in 1 new commits.

Change-Id: I1e317cf6ef4803577e9b353fb3313d001db228d7
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:46:18 +00:00
Angel Pons c8027454ba nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}
This allows us to drop some casts to uintptr_t around the tree.
The MCHBAR32 macro still needs a cast to preserve reproducibility.
Only the native raminit path needs the cast, the MRC path does not.

Tested with BUILD_TIMELESS=1, these boards remain identical:
 - Lenovo ThinkPad X230
 - Dell OptiPlex 9010
 - Roda RW11 (with MRC raminit)

Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:19 +00:00
Angel Pons 92717ff3e4 nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macro
RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.

Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:35:03 +00:00
Angel Pons 10240510a7 nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macro
This macro is unused, and RCBA is located in the PCH. Drop it.

Change-Id: Id7c095496360bbe96dc2a36dcc557a1481c02c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45347
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:34:54 +00:00
Michael Niewöhner 1d7b7f6e7a mb/system76/lemp9: move HDA options into devicetree
Change-Id: Id4fc12896f89739d0ee2a47a42173693921da14e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45132
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 19:24:30 +00:00
Shreesh Chhabbi 7fbcdb3f9a mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS based
platforms

BUG=b:145958015
TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin.

Cq-Depend:chrome-internal-review:3249528
Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-17 19:04:28 +00:00
nick_xr_chen 5200063114 mb/google/volteer/variants/eldrid: Configure DP_HPD as PAD_NC
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.

BUG=b:165893624, b:168090618

Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 18:20:53 +00:00
Elyes HAOUAS 72fc9a3e26 src: Remove redundant <device/pnp_type.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_type.h>.

Change-Id: I0e479e2abdb6cfb8633840db2222ce5397fe7d55
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45403
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 13:22:44 +00:00
Elyes HAOUAS 4b683b85a8 src: Remove redundant <device/pnp_def.h>
When <device/pnp.h> is needed, it is supposed to provide <device/pnp_def.h>.
So remove redundant <device/pnp_def.h> includes.
I'll remove also <device/pnp_type.h> in a separate patch.

Change-Id: Ib9903ae456c32db4ba346020659c17c27a939e89
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-17 13:21:48 +00:00
Rob Barnes 28cb14bf13 soc/amd/picasso: Clean up legacy UART config
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.

BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-09-17 12:35:56 +00:00
Michael Niewöhner 60795784b7 soc/intel/cannonlake: fix GPIO community numbering in ACPI
This corrects the GPIO community numbers in CNL-LP ACPI code.

Change-Id: I9f13a28d3e8f427859570a4d209304ae8444efd9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45209
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 10:36:31 +00:00
Subrata Banik 7938ebc7d7 soc/intel/common/block/chip: Refactor chip_get_common_soc_structure()
Found-by: Klocwork, Pointer soc_config is used uninitialized.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7e2aa4ef23a68a2ec2ba9d55cf890a7f81e3e278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-17 09:57:06 +00:00
Subrata Banik 754de4da37 soc/intel/common/block: Add NULL check for 'ctx' pointer
Found-by: Klocwork, Avoid NULL pointer (ctx) dereference.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I16015b538112e0b125b4a5e145c26263c456953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 09:56:56 +00:00
CK Hu 804b3bd10f soc/mediatek/mt8192: Init PLL in bootblock
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: If16d244e07d9f369efd991132587a92e38200b45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-17 06:56:55 +00:00
Weiyi Lu fd3c727ed9 soc/mediatek/mt8192: Add mtcmos init support
Using common mtcmos code to power on audio and display modules in SOC.

TEST=Boots correctly on MT8192EVB. Passes the status check at the end of
     mtcmos_power_on()

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ie7bff831eecfc2b4d315a577f6ff86befc483eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45394
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:56:31 +00:00
Chris Wang 7ef7596569 mb/google/zork: Add dptc interface support for morphius
Add dptc interface in devicetree for morphius.
Set the STAPM parameters for tablet mode:

    dptc_enable = 1
    dptc_fast_ppt_limit = 24000
    dptc_slow_ppt_limit = 20000
    dptc_sustained_power_limit = 6000

BUG=b:157943445
BRANCH=zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:19:07 +00:00
Chris Wang e019bd910f ec/google/chromeec: Add dptc interface support
add the dptc interface support when system in tablet mode.
In some FP5/FT5 platform, which will have different power or thermal
parameters depends on different form factor.

BUG=b:157943445
BRANCH=Zork
TEST=Build. check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I2be7942132cea474237f531021ad4fd9856b5050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17 06:18:59 +00:00
Chris Wang 4735b1c01b soc/amd/picasso: add dptc support
add dptc support for different power parameter on tablet/clamshell mode

The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing  the BIOS to request power state changes independently of specific
 events.

BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-17 06:05:27 +00:00
Angel Pons 2ce386a3c2 soc/intel/common/block: Do not die if PRMRR size unsupported
If a given PRMRR size is not supported, do NOT brick people's devices.
We don't do that when PRMRRs aren't even supported anyway.

Change-Id: Ib917be873aedbc5e789bb0894fca335b5ee9e2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-09-16 20:56:35 +00:00
Shelley Chen 2d90ddd2d2 region_file_update_data_arr: Modify region_file with array of buffers
Add region_file_update_data_arr, which has the same functionality as
region_file_update_data, but accepts mutliple data buffers.  This is
useful for when we have the mrc_metadata and data in non-contiguous
addresses, which is the case when we bypass the storing of mrc_cache
data into the cbmem.

BUG=b:150502246
BRANCH=None
TEST=reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Change-Id: Ia530f7d428b9b07ce3a73e348016038d9daf4c15
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45407
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 16:02:54 +00:00
Felix Held a79e01bf71 soc/amd/picasso/data_fabric: make register number parameter unsigned
The register number is always non-negative, so it should be an unsigned
type.

Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 14:47:15 +00:00
Felix Held bf90b14d6a soc/amd/picasso/data_fabric: include types.h
data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.

Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2020-09-16 14:47:04 +00:00
Marc Jones 5cb7599ca1 xeon_sp/skx: Reorder pci_devs.h
Reorder to be similar to cpx/include/soc/pci_devs.h.
We may be able to merge the files in the future.

Checked TiogaPass with BUILD_TIMELESS=1

Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45220
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:59 +00:00
Marc Jones 8015482f67 xeon_sp/cpx/pci_devs.h: Remove duplicate defines
Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 10:18:44 +00:00
Weiyi Lu 0fed84b8c4 soc/mediatek: move power status bits under each chip
The power status bits of display and audio of MT8192 are different
from the bits of MT8173 & MT8183, so move those under each chip.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Iaa211b8db733d8aa52d93af9e507042bf0984d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-09-16 07:48:20 +00:00
Pandya, Varshit B d121a117cc mb/google/dedede: Replace static Camera ACPI by driver for WDoo
This change updates devicetree to enable SSDT generation for world
facing camera and user facing camera of Waddledoo. Also reverts DSDT
changes related to both the camera.

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Ib7e875d297c04f35d4e980ff33d9a3767d2910ac
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-09-16 07:16:19 +00:00
Pandya, Varshit B cd91db953c drivers/intel/mipi_camera: Add compatible field for NVM
Add compatible field for NVM
Make PRP0001 as default HID if device type is INTEL_ACPI_CAMERA_NVM

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Iad7afa7b3170982eb5d6215e766f3e98f7a89213
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-09-16 07:16:09 +00:00
Ian Feng c410542007 mb/google/dedede/var/madoo: Enable keyboard backlight feature
This enables the keyboard backlight feature in ACPI for madoo.

BUG=b:167943993
TEST=Verified 'kbd_backlight' shows up in the '/sys/class/leds '.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I11531699cb650b96becae5c1bec9f89c48b6bea0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-09-16 07:15:05 +00:00
Caveh Jalali 8274c2926f drivers/spi/tpm: Improve error checking
This adds error checking in paths that previously ignored TPM
communication errors. We hit this case occasionally during "Checking
cr50 for pending updates"; previously we would go down this path and
eventually time out using MAX_STATUS_TIMEOUT, which is 2 minutes.
Now, we detect the failure and return with an error indication instead
of timing out after a long time. The root cause of the communication
error is an open issue.

BUG=b:168090038
TEST=booted on volteer, observed error handling when
	"Checking cr50 for pending updates" fails.

Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-16 07:14:40 +00:00
Angel Pons 0f651650f3 drivers/aspeed/common: Reduce severity of `EDID not found` log message
Servers often run headless, so a missing EDID isn't a problem. However,
we still need to initialize a framebuffer for the BMC's KVM function.

Reduce the log level to BIOS_INFO to avoid confusion.

Change-Id: Ice17bf6fdda0ce34e686dbf8f3a1fa92ba869d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-16 07:14:15 +00:00
Rob Barnes e5aa5ae1ba soc/amd/picasso: Convert DDR4 MHz to MT/s correctly
Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.

Use method from dram/ddr4.c instead.

BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
     and dmidecode -t17
BRANCH=Zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 03:25:28 +00:00
Rob Barnes a01ee36288 device/dram: Add method for converting MHz to MT/s
Add method for converting DDR4 speed in MHz to MT/s. Checks that MHz is
within a speed grade range.

BUG=b:167155849
TEST=ddr4-test unit test
BRANCH=Zork

Change-Id: I1433f028afb794fe3e397b03f5bd0565494c8130
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-16 03:24:50 +00:00
Lucas Chen fcd7d0518c zork/var/ezkinil: Fix Touchscreen doesn't work on v3.6x rework board
The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but
addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed.

BRANCH=zork
BUG=b:168580357
TEST=Check Touchscreen function work

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 02:04:25 +00:00
Ravi Kumar Bokka 9c0b8ef83c trogdor: invoke new watchdog function before qclib runs
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ia76323c749a9ba71cc752a91c968aeacc11e0093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45212
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16 00:44:18 +00:00
Ravi Kumar Bokka 6fde4c56b0 sc7180: report hardware watchdog reset after reboot
add WATCHDOG_TOMBSTONE in memlayout.ld

Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-16 00:44:09 +00:00
Felix Held 336ed66e35 soc/amd/stoneyridge/acpi/sb_pci0_fch: remove duplicate I/O range
This I/O region is already covered by the range declared right above the
deleted one.

Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:54 +00:00
Felix Held 4ed3116f33 soc/amd/picasso/acpi/sb_pci0_fch: remove duplicate I/O range reservation
This I/O region is already covered by the range declared right above the
deleted one.

TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork

Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 19:31:48 +00:00
Patrick Rudolph a1ef21301b nb/intel/ironlake/raminit: Work around compiler bug
This fixes commit e1d1fe454c
initialize 'reply.command'.

The compiler now optimized away the final condition, that checks
the result of heci message, resulting in a binary that always
calls die().

Fix that behaviour by using volatile.
Tested on Lenovo T410: Boots again into Linux.

Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 18:03:26 +00:00
Subrata Banik 292afef2fb soc/intel/alderlake/romstage: Do initial SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API

Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-15 15:13:50 +00:00
Subrata Banik eb17b475c8 mb/intel/jasperlake_rvp: Fix wrong comments for ECT
Disable -> Enable

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iccefb02fa9bf9507b9e679b3fba35c5c28d677a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-15 15:13:06 +00:00
Jason Glenesk 201acca634 acpi: Correct sizes for ACPI data fields
Correct sizes of Count, Type, and Latency data field in _CST object to
integer, byte, word, respectively. Correct size of NumEntries data field
in _CSD object to integer.

BUG=b:155307433
TEST=Boot Morphius and dump SSDT _CST and _CSD objects. Confirm that
sizes written conform to ACPI_6_3_May16.pdf ACPI specification.
BRANCH=Zork

Change-Id: I356b46f2fa787e18442a66280b6545a3b525a08b
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45339
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 13:41:58 +00:00
Patrick Rudolph 11c1b94d03 soc/intel/common/block/cpu: Fix boot failure
This fixes commit 1b89f5e "Guard options with if-blocks".

The code no longer returns if SGX is disabled, but as the PRMRR
configuration is missing it runs into die().

Tested on Prodrive Hermes: Boots again into Linux.

Change-Id: I6d32ca32b1b53767b2db91305103cd532823a5ca
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-15 09:17:58 +00:00
V Sowmya 186250f68e common/block/pmc: Add a check to program the PchPmPwrCycDur
This patch adds a check to avoid violating the PCH EDS recommendation
that the PchPmPwrCycDur will never be smaller than the the SLP_Sx
assertion widths.

This code was initially added for cannonlake and now moving it to common
code since the same check will be used to program the PchPmPwrCycDur
for Jasperlake and Tigerlake.

Change-Id: Ie7d5f54939c5eb1f885d303f75a04958b9d77f4d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:02:04 +00:00
Ren Kuo 98b0a98891 mb/google/dedede/var/magolor: Add touch screen devices
add the magolor touch screen ctrl devices:
1)elan 6915
2)elan 5012
3)raydium RM32680

BUG=b:166711761
BRANCH=None
TEST=build firmware and verify the touch functions on DUT

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Icd2963317e858f7d35c937e45cd6f3e556bbb953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45227
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 07:01:29 +00:00
Furquan Shaikh b0334e13ba mb/google/zork: Fix FPMCU_INT_L configuration
Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge
triggered. Also, we are using GEVENT for wake from fingerprint and
not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables
does not need to be set to indicate wake for the IRQ.

This change updates GPIO table to configure the pad as level triggered
and drops the wake attribute for irq_gpio in overridetree.

BUG=b:165612778
BRANCH=zork
TEST=Verified that fingerprint still works in S0 and to wake device
from S3.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-09-15 03:57:43 +00:00
Ravi Kumar Bokka 5ed3cb99ac chromeos: Provide common watchdog reboot support in romstage
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I2a1f1411e9d58a0738e0e8057f5b1ad049bf03e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15 01:09:38 +00:00
Taniya Das 4236187dea sc7180: clock: Remove unwanted QUPv3 Frequency
As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.

Tested: Compile and boot up testing.

Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:27 +00:00
Roja Rani Yarubandi dcf80ab025 sc7180: Remove QcLib specific changes from CB UART
To achieve 115200 baudrate QcLib reconfigures UART frequency
with the lowest supported frequency from QUP clock table.
With this console logs were getting corrupted at qclib stage.

In ChromeOS coreboot, baudrate is configuarable using Kconfig.
QcLib should not assume the baudrate and reconfigure any UART
register once after the configuration is done in coreboot.

To fix the issue QcLib done the changes to not to reconfigure
any UART registers. Hence clock_configure_qup() is not required
in coreboot UART driver.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Change-Id: I2531b64eddfa6e877f769af0d17be61f5e4d0c35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-15 01:07:17 +00:00
Nico Huber 308540de80 nb/intel/ironlake: Reserve gap betwen TSEG and BGSM
There may be a gap between TSEG and the graphics stolen memory due to
the alignment done in `raminit.c`. If we allocate MMIO resources in
this range, it misbehaves unpredictably, so reserve it.

TEST=Booted Thinkpad X201s, allocated resources are above TOLUD.

Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14 20:15:06 +00:00